Methods for electrochemically fabricating structures using adhered masks, incorporating dielectric sheets, and/or seed layers that are partially removed via planarization

• US 7,501,328 B2
• Filed: 05/26/2005
• Issued: 03/10/2009
• Est. Priority Date: 05/07/2003
• Status: Active Grant

• Current Assignee: Microfabrica Incorporated (Technoprobe S.P.A.)
• Original Assignee: Microfabrica Incorporated (Technoprobe S.P.A.)
• Inventors: Smalley, Dennis R., Lockard, Michael S., Chen, Richard T., Larsen, Willa M.
• Primary Examiner(s): Toledo; Fernando L
• Application Number:
  US11/139,262
• Publication Number:
  US 20060011486A1
• Time in Patent Office: 1,384 Days
• Field of Search: 438/466, 438/469, 438/652, 438/666
• US Class Current: 438/466
• CPC Class Codes: B33Y 10/00 Processes of additive manufacturing
• CPC Class Codes: B81C 1/00492 Processes for surface micromachining not provided for in groups B81C1/0046 - B81C1/00484
• CPC Class Codes: C23C 18/1605 by masking
• CPC Class Codes: C25D 1/003 3D structures, e.g. superposed patterned layers
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: Y10T 156/10 Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 156/1041 Subsequent to lamination

Abstract

Embodiments of the present invention provide mesoscale or microscale three-dimensional structures (e.g. components, device, and the like). Embodiments relate to one or more of (1) the formation of such structures which incorporate sheets of dielectric material and/or wherein seed layer material used to allow electrodeposition over dielectric material is removed via planarization operations; (2) the formation of such structures wherein masks used for at least some selective patterning operations are obtained through transfer plating of masking material to a surface of a substrate or previously formed layer, and/or (3) the formation of such structures wherein masks used for forming at least portions of some layers are patterned on the build surface directly from data representing the mask configuration, e.g. in some embodiments mask patterning is achieved by selectively dispensing material via a computer controlled inkjet nozzle or array or via a computer controlled extrusion device.

Claims

1. A process for forming a multilayer three-dimensional structure, comprising:

(a) forming and adhering a layer of material to a substrate, wherein the substrate may include previously formed layers; and

(b) repeating the forming and adhering operation of (a) a plurality of times to build up a three-dimensional structure from a plurality of adhered layers;

wherein the formation of at least one layer comprises;

(i) forming a desired pattern of dielectric material on the substrate or on previously deposited material wherein the patterning of the dielectric results in at least one void in the dielectric material that exposes a portion of the substrate or previously deposited material;

(ii) applying a seed layer material to the dielectric material;

(iii) depositing a conductive material into the at least one void in the dielectric; and

(iv) after depositing the conductive material, removing at least a portion of the seed layer material located on the dielectric material

(v) selectively etching into the conductive material to form at least one second void;

(vi) depositing a seed layer into the at least second void; and

(vii) depositing a second conductive material into the at least one second void.

2. A process for forming a multilayer thee-dimensional structure, comprising:

(a) forming and adhering a layer of material to a substrate, wherein the substrate may include previously formed layers; and

(b) repeating the forming and adhering operation of (a) a plurality of times to build up a three-dimensional structure from a plurality of adhered layers;

wherein the formation of at list one layer comprises;

(i) forming a desired pattern of a first material on the substrate or on previously deposited material; and

thereafter applying a non-planar seed layer material which will be used as based onto which a second material will be subsequently electrodeposited;

(ii) after deposition of the second material, removing at least portion of the deposition material and a portion of the non-planar seed layer while planarizing a surface of the first and second material,

(iii) after planarizing, the first or second material is at least partially removed to create voids in preparation for deposition third material,

(iv) depositing a second seed layer material in the voids created in preparation for deposition of the third material; and

(v) electrodepositing a third material over wherein the third material is a conductive material that is electrodeposition over the second seed layer material, wherein the third material is a conductive material; and

(vi) after deposition of the third material, planarizing at least a portion of a least one of first, second, or third materials.

3. The process of claim 2 wherein at least one of the first, second, or third material is a dielectric material comprising at least one of:

a photoresist, a polyimide, a glass, a ceramic, a dielectric having a dielectric constant less than about 3.0, Futurrex Protective Barrier Coating 3-6000, Shipley Intervia™

Photodielectric Material 8010, Shipley Intervia™

Photodielectric Material 8021, or Shipley BPR 100 Photoresist.