Level shifter circuit

• US 7,501,876 B2
• Filed: 10/17/2007
• Issued: 03/10/2009
• Est. Priority Date: 11/22/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kimura, Hiroyuki
• Primary Examiner(s): Nguyen; Long
• Assistant Examiner(s): Cole; Brandon S
• Application Number:
  US11/873,424
• Publication Number:
  US 20080164931A1
• Time in Patent Office: 510 Days
• Field of Search: 326/62, 326/63, 326/68, 326/80, 326/81, 327/333, 365/189.11
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A level shifter circuit that properly operates even when the power supply voltage is unstable. A level shifter circuit includes a first level shifter unit, a second level shifter unit, and a latch unit. In the first level shifter unit, a transistor is connected to a power supply line to generate drive voltage that is lower than a first power supply voltage. The first level shifter unit outputs complementary signals from the drive voltage. The output of the first level shifter unit is provided to the second level shifter unit. The second level shifter unit converts a complementary signal to a signal having a second power supply voltage. Based on this signal, a signal of the latch unit is switched.

Claims

1. A level shifter circuit, comprising:

a first voltage conversion circuit for generating a drive voltage that is lower than a first power supply voltage supplied from a first power supply line and is in correspondence with the first power supply voltage, and generating and outputting complementary signals corresponding to an input signal using the drive voltage;

a second voltage conversion circuit, connected to the first voltage conversion circuit, for generating and outputting a signal corresponding to voltages of the complementary signals output from the first voltage conversion circuit using a second power supply voltage supplied from a second power supply line; and

an output latch circuit, connected to the second voltage conversion circuit, for receiving and holding the signal output from the second voltage conversion circuit,

wherein the first voltage conversion circuit includes;

a first transistor having a gate, a drain and a source, wherein the gate and drain are connected to the first power supply line, and the drive voltage is output at the source; and

a differential amplifier, connected to the first transistor, for generating the complementary signals corresponding to the input signal and an inverted input signal using the drive voltage output by the first transistor, and wherein the differential amplifier includes;

a second transistor having a source connected to the source of the first transistor;

a third transistor having a source connected to the source of the first transistor and a gate connected to a drain of the second transistor, and a drain connected to a gate of the second transistor;

a fourth transistor having a drain connected to the drain of the second transistor, a gate that receives the inverted input signal, and a source connected to a common line; and

a fifth transistor having a drain connected to the drain of the third transistor, a gate that receives the input signal, and a source connected to the common line, wherein the drain terminals of the fourth and fifth transistors output the complementary signals provided to the second voltage conversion circuit.

2. The level shifter circuit of claim 1, wherein the first, fourth and fifth transistors are NMOS transistors and the second and third transistors are PMOS transistors.

3. The level shifter circuit of claim 1, wherein the second voltage conversion circuit includes:

a sixth transistor having a source connected to the second power supply line;

a seventh transistor having a source connected to the second power supply line, a gate terminal connected to a drain terminal of the sixth transistor, and a drain connected to a gate of the sixth transistor;

an eighth transistor having a drain connected to the drain of the sixth transistor and a gate connected to the first power supply line;

a ninth transistor having a drain connected to the drain of the seventh transistor and a gate connected to the first power supply line;

a tenth transistor having a drain connected to a source of the eighth transistor, a drain connected to the common line, and a gate that receives one of the complementary signals form the first voltage conversion circuit; and

an eleventh transistor having a drain connected to a source of the ninth transistor, a drain connected to the common line, and a gate that receives the other one of the complementary signals from the first voltage conversion circuit.

4. The voltage conversion circuit of claim 3, wherein the sixth and seventh transistors are PMOS transistors and the eighth through eleventh transistors are NMOS transistors.

5. The voltage conversion circuit of claim 1, wherein the second voltage conversion circuit includes:

a sixth transistor having a source connected to the second power supply line;

a seventh transistor having a source connected to the second power supply line, a gate terminal connected to a drain terminal of the sixth transistor, and a drain connected to a gate of the sixth transistor;

a twelfth transistor having a drain connected to the drain of the sixth transistor and a gate that receives one of the complementary signals;

a thirteenth transistor having a drain connected to the drain of the seventh transistor and a gate that receives the other one of the complementary signals; and

a fourteenth transistor having a drain connected to the sources of the twelfth and thirteenth transistors, a source connected to the common line and a gate connected to the first power supply line.

6. The voltage conversion circuit of claim 5, wherein the sixth and seventh transistors are PMOS transistors and the twelfth through fourteenth transistors are NMOS transistors.