In-plane switching liquid crystal display and driving method thereof

• US 7,502,087 B2
• Filed: 05/23/2005
• Issued: 03/10/2009
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kang, Byung Koo, Kim, Do Sung
• Primary Examiner(s): Caley; Michael H
• Application Number:
  US11/134,280
• Publication Number:
  US 20050264744A1
• Time in Patent Office: 1,387 Days
• Field of Search: 349/141, 349/145, 349/146, 349/147
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

An in-plane switching LCD including a plurality of gate and data lines crossing each other to define a plurality of pixel areas; a thin film transistor formed at a crossing of the data and gate lines; a pair of common lines facing each other and substantially parallel to the data lines in the pixel areas; a common electrode integrally formed with the common lines, the common electrode being inclined by a predetermined angle; a pair of pixel electrode lines overlapping the common lines; and a pixel electrode integrally formed with the pixel electrode lines, the pixel electrode being inclined substantially parallel to the common electrode, the pixel electrode being arranged in an alternating pattern with the common electrode, wherein the gate lines are formed substantially parallel to the common electrode and the pixel electrode.

Claims

1. An in-plane switching liquid crystal display comprising:

a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of pixel areas, the data lines having a straight line respectively;

a thin film transistor formed at a crossing of the data and gate lines, wherein each thin film transistor is alternately disposed on a left pixel area and a right pixel area of the data line according to a pixel column to have a zigzag shape, the pixel column including the pixel areas parallel to the data line;

a pair of common lines facing each other and substantially parallel to the data lines in the pixel areas;

a common electrode integrally formed with the common lines, the common electrode being inclined by a predetermined angle;

a pair of pixel electrode lines overlapping the common lines and substantially parallel to the common lines; and

a pixel electrode integrally formed with the pixel electrode lines, the pixel electrode being inclined substantially parallel to the common electrode, the pixel electrode being arranged in an alternating pattern with the common electrode,

wherein the common electrode and the pixel electrode each is symmetrically inclined with respect to a center line of the pixel area, the center line being a direction perpendicular to the data line, and

wherein the gate lines are formed substantially parallel to the common electrode and the pixel electrode in each pixel area.

2. The display according to claim 1, wherein the gate lines are inclined substantially parallel to the common electrode and the pixel electrode, wherein an aperture ratio is increased at the crossing of the data and gate lines.

3. The display according to claim 1, wherein the common electrode inclines upward in a upper pixel area of the center line and inclines downward in a lower pixel area of the center line.

4. The display according to claim 1, wherein the pixel electrode inclines upward in a upper pixel area of the center line and inclines downward in a lower pixel area of the center line.

5. The display according to claim 1, wherein a storage capacitance is formed in a region Where the common lines and the pixel electrode lines overlap with each other.

6. The display according to claim 1, wherein the gate lines, the common electrode, and the pixel electrode are arranged to incline by a same angle and to be substantially parallel to one another in the pixel areas.

7. The display according to claim 1, wherein the gate lines, the common electrode, and the pixel electrode are arranged to incline by an angle of below about 45°

with respect to the center line.

8. The display according to claim 1, wherein the common lines are formed to have a width of about 8 μ

m or below.

9. The display according to claim 1, wherein distances of the gate lines extend from each other so as to widen an opening area of each pixel area.

10. The display according to claim 1, wherein pixel electrodes are spaced apart from each other by a predetermined interval in the pixel areas.

11. The display according to claim 10, wherein the pixel electrodes are spaced apart from each other by a predetermined interval of about 10 μ

m in the pixel areas.

12. The display according to claim 1, wherein the pixel areas include the thin film transistors display image of dot inversion type in response to data signals of column inversion type.