Flash memory cell arrays having dual control gates per memory cell charge storage element
First Claim
1. A non-volatile memory for programming and reading data, comprising:
- a plurality of charge storage elements arranged in rows and columns across a semiconductor substrate,a plurality of control gate lines extending across the charge storage elements in a manner that opposing sidewalls on opposite sides of individual charge storage elements are capacitively coupled with at least two of the control gate lines, anda decoder and voltage supply connected to the control gate lines to couple controlled voltages to the charge storage elements capacitively coupled therewith during programming data thereto and reading data therefrom.
2 Assignments
0 Petitions
Accused Products
Abstract
A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
-
Citations
13 Claims
-
1. A non-volatile memory for programming and reading data, comprising:
-
a plurality of charge storage elements arranged in rows and columns across a semiconductor substrate, a plurality of control gate lines extending across the charge storage elements in a manner that opposing sidewalls on opposite sides of individual charge storage elements are capacitively coupled with at least two of the control gate lines, and a decoder and voltage supply connected to the control gate lines to couple controlled voltages to the charge storage elements capacitively coupled therewith during programming data thereto and reading data therefrom. - View Dependent Claims (2, 3, 4, 5, 12)
-
-
6. A non-volatile memory for programming and reading data, comprising:
-
an array of charge storage elements positioned across a semiconductor substrate, a plurality of control gate lines extending across the array in a manner that opposing sidewalls of individual charge storage elements are capactively coupled with at least two of the control gate lines, and a decoder and voltage supply connected to the control gate lines to couple controlled voltages to the charge storage elements capactively coupled therewith during programming data thereto and reading data therefrom, wherein the memory cells are oriented in a plurality of series connected strings of memory cells, and wherein the control gates extend across multiple strings of memory cells between the charge storage elements, and wherein the control gates include a combination of doped polysilicon as a bottom portion of a height of the control gates and a metal or silicide material in contact therewith as a top portion of the height of the control gates.
-
-
7. A non-volatile memory for programming and reading data, comprising:
-
a plurality of charge storage elements positioned across a semiconductor substrate with rows of the charge storage elements extending in a first direction and columns of charge storage elements extending in a second direction, the first and second directions being perpendicular with each other, a plurality of control gate lines extending across the plurality of charge storage elements in the first direction and being spaced apart in the second direction between adjacent rows of charge storage elements in a manner that opposing sidewalls on opposite sides of individual charge storage elements of the rows are capacitively coupled with at least two control gate lines on opposite sides of the charge storage elements, and a decoder and voltage supply connected to the control gate lines to couple controlled voltages to the charge storage elements capacitively coupled therewith during programming data thereto and reading data therefrom. - View Dependent Claims (8, 9, 10, 11, 13)
-
Specification