Code coverage testing in hardware emulation

• US 7,502,728 B1
• Filed: 12/20/2002
• Issued: 03/10/2009
• Est. Priority Date: 04/30/2002
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Nilson, Arthur J., Kun, Stephen, Hurlock, Steven T., Nichols, Jeremy S., Johnson, Robert A.
• Primary Examiner(s): Shah; Kamini S
• Assistant Examiner(s): Gebresilassie; Kibrom K
• Application Number:
  US10/324,462
• Time in Patent Office: 2,272 Days
• Field of Search: 703/23, 703 13- 16, 717/106, 717/122, 717/134, 717/115, 717/124, 717/130, 717/138, 717/30, 717/126, 717/135, 717/141, 717/154, 717/158, 714/30
• US Class Current: 703/23
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Code coverage questions are addressed by a code coverage method that instruments an electronic module source design file with coverage probes and gives hierarchical names to the probes, then provides therefrom an instrumented gate level netlist. The instrumented netlist is run on a hardware emulator, executing reset trigger scripts to reset the branch and statement probes, and then a fully initialized design is driven in emulation on a simulated testbench from which the probe values are retrieved. These values can then be evaluated to determine the extent of code coverage. Various forms of coverage are supported including branch, statement, reset trigger and toggle coverage.

Claims

1. A computer-implemented method of providing code coverage testing for use in emulation of a logic circuit design having a plurality of logic gates, the logic design represented as a plurality of modules in a source code design file, the method comprising:

instrumenting a selected module of the source design file with coverage probes by instantiating a probe for each gate output;

generating a hierarchical name list comprising a hierarchical name for each instantiated probe;

generating a history template file from the hierarchical name list;

compiling/synthesizing the instrumented source file into an instrumented gate-level netlist;

generating two scripts using the list of hierarchical names from the history template file, wherein the two scripts comprise a reset trigger script and a probe value extraction script;

loading the instrumented gate-level netlist onto a hardware emulator;

initializing an emulation run and executing the reset trigger script to reset all branch and statement probes;

driving the fully initialized design in emulation by a simulated testbench;

running the generated extraction script to retrieve the probe values from

the testbench emulation, wherein the retrieved probe values are used in code coverage testing;

generating a temporary file to hold the retrieved probe values;

populating the temporary file with the retrieved probe values;

merging the history template file with the retrieved probe values from the temporary file to produce a first history file;

finding unexercised logic using the instrumented gate-level netlist and generating a second history file;

merging the first history file with the second history file to produce code coverage results; and

producing a code coverage tool report using the code coverage results.

2. The method of claim 1 further comprising, saving the extracted probe values in a valid input format for use by a code coverage tool.

3. The method of claim 2 further comprising, examining said extracted probe values in said code coverage tool to determine which instantiated probe outputs are unexercised.

4. The method of claim 3 further comprising, producing, by the code coverage tool, reports that detail an amount of the design that has been exercised.

5. The method of claim 1 wherein an appropriately sized module is selected for said source design file.

6. The method of claim 1 wherein there are three types of probes instantiated, branch probes, statement probes, and toggle probes.

7. The method of claim 6 wherein at least one instantiated probe is a statement probe and wherein said statement probe is activated when the any signal in a sensitivity list of said at least one instantiated statement probe change.

8. The method of claim 7 wherein said sensitivity list is a list of gates that are affected by the output of at least one other gate.

9. The method of claim 8 wherein said sensitivity list has also stored an initial value of all signals in the sensitivity list for said at least one instrumented statement probe, and by providing a comparison mechanism to cause said at least one instrumented statement probe to activate when the current and initial value of the sensitivity list are not equal.

10. The method of claim 6 wherein said trigger probe is instantiated once per instrumented module and is provided with one control port to all other instrumented probes in the module design file.

11. The method of claim 10 wherein said trigger probe provides a reset signal to all resettable instrumented probes.

12. The method of claim 10 wherein said trigger probe provides an enable_capture/enable_compare signal pair for statement probe instantiations.

13. The method of claim 6 wherein said toggle probes checks whether a given signal received in a toggle probe instantiation has made a high to low transition and a low high transition.

14. The method of claim 13 wherein implementation of a toggle probe comprises the use of two components, wherein each component has a signal of interest as an input and has an edge triggered latch, and wherein the latch in one component is set by a rising edge on its input signal, and wherein the other is set by a falling edge on its input signal.

15. A code coverage tool as set forth in claim 1 having one or more of the following:

Branch coverage for use including one or more of the following types of branch coverage, standard, for-generate, and for-loop, Statement coverage, A reset trigger, and Toggle coverage.

16. A computer-implemented method of employing code coverage testing of a logic circuit design comprising a plurality of logic gates, the logic design represented as a plurality of modules in a source code design file, the method comprising:

using a design source file and instrumenting the design with coverage probes;

generating a hierarchical name list comprising a hierarchical name for each instantiated probe;

generating a history template file from the hierarchical name list;

compiling/synthesizing the instrumented design source file into a gate-level netlist, the list of hierarchical names from the history template file is used to generate two scripts comprising a reset trigger script to initiate coverage testing and a probe extraction script;

generating a temporary file to hold extracted probe values;

running the gate-level netlist in a hardware emulator with the two scripts saving the extracted probe values in the temporary file;

merging the history template file and the extracted probe values from the temporary file to produce a first history file;

finding uncovered logic using the gate-level netlist and generating a second history file;

merging the first history file with the second history file to produce code coverage results having a valid input format for use by a code coverage tool; and

producing reports by the code coverage tool.

17. The method of claim 16 wherein at least one of said reports produced by said code coverage tool wherein unexercised logic is identified.

18. A software storage disk comprising computer-executable operating instructions adapted to configure a computer system already capable of running a hardware emulation of a logic circuit design as a code coverage tool when loaded into said computer system, when said computer system is so configured, being operable as a code coverage tool during running of said hardware emulation and in such operation, determining which logic being so emulated is covered, and specifically wherein the operating instructions comprise instructions which, when executed, perform operations comprising:

instrumenting a design source file with instantiated coverage probes generating an instrumented design source file;

generating a hierarchical name list comprising a hierarchical name for each instantiated probe;

generating a history template file from the hierarchical name list;

compiling/synthesizing the instrumented design source file into a gate level netlist, the hierarchical name list names from the history template file used to generate two scripts comprising a reset trigger script to initiate coverage testing and a probe extraction script;

generating a temporary file to hold extracted probe values;

running the gate-level netlist in a hardware emulator with the two scripts saving the extracted probe values in the temporary file;

merging the history template file and the extracted probe values from the temporary file to produce a first history file;

finding uncovered logic using the gate-level netlist and generating a second history file;

merging the first history file with the second history file to produce code coverage results having a valid input format for use by a code coverage tool; and

producing reports by the code coverage tool.