Intelligent network interface system and method for accelerated protocol processing

• US 7,502,869 B2
• Filed: 11/28/2003
• Issued: 03/10/2009
• Est. Priority Date: 10/14/1997
• Status: Expired due to Fees

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Higgen, David A., Philbrick, Clive M., Boucher, Laurence B., Craft, Peter K., Blightman, Stephen E. J., Starr, Daryl D.
• Primary Examiner(s): LIN, WEN TAI
• Application Number:
  US10/724,588
• Publication Number:
  US 20040111535A1
• Time in Patent Office: 1,929 Days
• Field of Search: 709249-250, 709/203, 709/228, 370401-404
• US Class Current: 709/250
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/245 Link aggregation, e.g. trunking
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 67/62 Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/168 specially adapted for link layer protocols, e.g. asynchronous transfer mode [ATM], synchronous optical network [SONET] or point-to-point protocol [PPP]
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04Q 2213/13093 : Personal computer, PC
• CPC Class Codes: H04Q 2213/13103 : Memory
• CPC Class Codes: H04Q 2213/13204 : Protocols
• CPC Class Codes: H04Q 2213/13299 : Bus
• CPC Class Codes: H04Q 2213/1332 : Logic circuits
• CPC Class Codes: H04Q 2213/13345 : Intelligent networks, SCP
• CPC Class Codes: H04Q 3/0029 : Provisions for intelligent networking

Abstract

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The CPD provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The CPD also assists the host CPU for those message packets that are chosen for processing by host software layers. A context for a message is defined that allows DMA controllers of the CPD to move data, free of headers, directly to or from a destination or source in the host. The context can be stored as a communication control block (CCB) that is controlled by either the CPD or by the host CPU. The CPD contains specialized hardware circuits that process media access control, network and transport layer headers of a packet received from the network, saving the host CPU from that processing for fast-path messages.

Claims

1. A system for communication between by a local host that is connectable by a network to a remote host, the system comprising:

a communication processing device (CPD) that is integrated into the local host to connect the network and the local host, said CPD including hardware configured to analyze Internet Protocol (IP) and Transmission Control Protocol (TCP) headers of network packets, and

a central processing unit (CPU) running protocol processing instructions in the local host to create a TCP connection between the local host and the remote host, said CPU providing to said CPD a media-access control (MAC) address, an IP address and a TCP port that correspond to said connection, wherein said CPD and said CPU are configured such that a message transferred between the network and the local host is generally processed by said CPD instead of said CPU when said CPD controls said connection and said message corresponds to said connection.

2. The system of claim 1, wherein said CPU provides to said CPD an address in local host memory for storing application data from said message.

3. The system of claim 1, wherein said CPU provides to said CPD an address in local host memory for retrieving application data corresponding to said connection.

4. The system of claim 1, wherein said CPD is connected to said CPU by a bus.

5. The system of claim 1, wherein said CPD includes a microprocessor.

6. The system of claim 1, wherein said CPD is connected to an input/output (I/O) controller.

7. The system of claim 6, wherein said I/O controller is a peripheral component interconnect (PCI) bridge.

8. The system of claim 1, further comprising a memory that is disposed in said host and accessible by said CPU and said CPD.

9. The system of claim 1, wherein said CPD is integrated with a peripheral component interconnect (PCI) bridge.

10. The system of claim 1, wherein said CPD is integrated with a memory controller for said CPU.

11. The system of claim 1, wherein said CPD is integrated with an I/O controller and a memory controller for said CPU.

12. The system of claim 1, wherein said CPD is connected with an I/O controller that connects said CPD to a memory controller for said CPU.

13. The system of claim 1, wherein said CPD is connected to a hub interface bus that connects a memory controller to an I/O controller.

14. The system of claim 1, wherein said message is received from the network by the local host.

15. A system for communication by a local host that is connectable by a network to a remote host, the system comprising:

a communication processing device (CPD) that is integrated into the local host to connect the network and the local host, said CPD including hardware configured to analyze Internet Protocol (IP) and Transmission Control Protocol (TCP) headers of network packets, and

a central processing unit (CPU) running protocol processing instructions in the local host to create a TCP connection between the local host and the remote host, said CPU providing to said CPD a media-access control (MAC) address, an IP address and a TCP port that correspond to said connection, wherein said CPD and said CPU are configured such that a packet transferred between the network and the local host is processed by said CPD and not by said CPU when said CPD controls said connection and said packet corresponds to said connection.

16. The system of claim 15, wherein said CPD is connected to said CPU by a bus.

17. The system of claim 15, wherein said CPD includes a microprocessor.

18. The system of claim 15, wherein said CPD is connected to an input/output (I/O) controller.

19. The system of claim 15, wherein said CPD is connected to a peripheral component interconnect (PCI) bridge.

20. The system of claim 15, further comprising a memory that is disposed in said host and accessible by said CPU and said CPD.

21. The system of claim 15, wherein said CPD is integrated with a peripheral component interconnect (PCI) bridge.

22. The system of claim 15, wherein said CPD is integrated with a memory controller for said CPU.

23. The system of claim 15, wherein said CPD is integrated with an I/O controller and a memory controller for said CPU.

24. The system of claim 15, wherein said CPD is connected with an I/O controller that connects said CPD to a memory controller for said CPU.

25. The system of claim 15, wherein said CPD is connected to a hub interface bus that connects a memory controller to an I/O controller.

26. The system of claim 15, further comprising an ownership bit disposed in the local host, said ownership bit designating whether said CPU or said CPD controls said connection.

27. The system of claim 15, wherein said packet is received from the network by the local host.

28. A system for communication by a local host that is connectable by a network to a remote host, the system comprising:

a central processing unit (CPU) disposed in the local host and running protocol processing instructions to create a Transmission Control Protocol (TCP) connection between the local host and the remote host, said CPU processing a first network packet corresponding to said connection; and

a communication processing device (CPD) integrated into the local host and connected to the network, said CPU providing to said CPD a media-access control (MAC) address, an Internet Protocol (IP) address and a Transmission Control Protocol (TCP) port that correspond to said connection, said CPD receiving control of said connection from said CPU, said CPD classifying a second network packet as corresponding to said connection and processing said second network packet without any protocol processing of said second network packet by said CPU.

29. The system of claim 28, wherein said CPD is connected to said CPU by a bus.

30. The system of claim 28, wherein said CPD includes a microprocessor.

31. The system of claim 28, wherein said CPD is connected to an input/output (I/O) controller.

32. The system of claim 28, wherein said CPD is connected to a peripheral component interconnect (PCI) bridge.

33. The system of claim 28, further comprising a memory that is accessible by said CPU and said CPD.

34. The system of claim 28, wherein said CPD is integrated with a peripheral component interconnect (PCI) bridge.

35. The system of claim 28, wherein said CPD is integrated with a memory controller for said CPU.

36. The system of claim 28, wherein said CPD is integrated with an I/O controller and a memory controller for said CPU.

37. The system of claim 28, wherein said CPD is connected with an I/O controller that connects said CPD to a memory controller for said CPU.

38. The system of claim 28, wherein said CPD is connected to a hub interface bus that connects a memory controller to an I/O controller.

39. The system of claim 28, further comprising an ownership bit disposed in the local host, said ownership bit designating whether said CPU or said CPD controls said connection.

40. The system of claim 28, wherein said second network packet is received from the network by the local host.