Memory device and memory card

• US 7,502,970 B2
• Filed: 07/14/2004
• Issued: 03/10/2009
• Est. Priority Date: 07/18/2003
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aizawa, Hideo
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US10/890,174
• Publication Number:
  US 20050041553A1
• Time in Patent Office: 1,700 Days
• Field of Search: 714/42, 714/48, 714/54, 714/719, 714/723
• US Class Current: 714/42
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A memory device comprises a data storage section, a section which compares in write processing, for data being target of the write processing, a state before the data is stored in the data storage section with a state of the data which is stored in the data storage section and read out from the data storage section, a section which obtains the number of errors for the write processing on the basis of a comparison result from the comparison section, and a section which returns the number of errors.

Claims

1. A memory device comprising:

a data storage section;

a comparison section which compares in write processing, for data being target of the write processing, a state before the data is stored in the data storage section with a state of the data which is stored in the data storage section and read out from the data storage section, and compares in erase processing, for a data block being target of erase processing of the data storage section, an actual state of the data block after the erase processing is executed with a theoretical data state after the erase processing is executed;

a section which obtains a first number of errors which is the number of bits which do not coincide or the number of error byte units in which incoincidence occurs for the write processing, and obtains a second number of errors which is the number of bits which do not coincide or the number of error byte units in which incoincidence occurs for the erase processing on the basis of a comparison result from the comparison section; and

a section which returns the first number of errors to a host device for the write processing, and returns the second number of errors to the host device for the erase processing.

2. A device according to claim 1, wherein the first and second numbers of errors are the number of 1-byte units in which incoincidence occurs.

3. A device according to claim 1, wherein the first and second numbers of errors are the number of 2-byte units in which incoincidence occurs.

4. A device according to claim 1, further comprising a section which stores a first allowable value representing a first allowable range of the first number of errors for the write processing and a second allowable value representing a second allowable range of the second number of errors for the erase processing, and

a section which validates the write processing for the data storage section when the number of errors falls within the first allowable range and invalidates the write processing for the data storage section when the first number of errors falls outside the first allowable range, and validates the erase processing for the data storage section when the second number of errors falls within the second allowable range and invalidates the erase processing for the data storage section when the second number of errors falls outside the second allowable range.

5. A device according to claim 4, wherein the first allowable value is set on the basis of an error-correctable number.

6. A device according to claim 1, wherein the data storage section is a NAND memory.

7. A memory device comprising:

a data storage section;

a section which stores a signal representing whether a write processing for the data storage section is normal for each of units which are obtained by dividing data being target of the write processing by a predetermined data length for the write processing, and whether erase processing for the data storage section is normal for each of units which are obtained by dividing a data block being target of the erase processing by the predetermined data length for the erase processing;

a section which stores a first allowable value representing a first allowable range of a first number of abnormal signals representing that the write processing for the data storage section is abnormal, and stores a second allowable value representing a second allowable range of a second number of abnormal signals representing that the erase processing for the data storage section is abnormal;

a section which returns the first number of abnormal signals to a host device for the write processing, and returns the second number of abnormal signals to the host device for the erase processing; and

a section which invalidates the write processing when the first number of abnormal signals of the signals falls outside the first allowable range for the write processing, and invalidates the erase processing when the second number of abnormal signals of the signals falls outside the second allowable range for the erase processing,

wherein the first and second allowable values are set from outside, and

the predetermined data length is a bit or byte unit.

8. A device according to claim 7, wherein the allowable value is set on the basis of an error-correctable number.

9. A device according to claim 7, wherein the data storage section is a NAND memory.

10. A memory card comprising:

an non-volatile semiconductor memory; and

a controller which executes write processing for the non-volatile semiconductor memory,

wherein the non-volatile semiconductor memory comprising;

a data storage section;

a comparison section which compares in write processing, for data being target of the write processing, a state before the data is stored in the data storage section with a state of the data which is stored in the data storage section and read out from the data storage section, and compares in erase processing, for a data block being target of erase processing of the data storage section, an actual state of the data block after the erase processing is executed with a theoretical data state after the erase processing is executed;

a section which obtains a first number of errors which is the number of bits which do not coincide or the number of error byte units in which incoincidence occurs for the write processing, and obtains a second number of errors which is the number of bits which do not coincide or the number of error byte units in which incoincidence occurs for the erase processing on the basis of a comparison result from the comparison section; and

a section which returns the first number of errors to a host device for the write processing, and returns the second number of errors to the host device for the erase processing.