Method and apparatus for detecting presence of errors in data transmitted between components in a data storage system using an I2C protocol

• US 7,502,992 B2
• Filed: 03/31/2006
• Issued: 03/10/2009
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Strickland, Stephen, Sullivan, Douglas, Leef, Phillip, Sanville, Alex
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US11/394,919
• Publication Number:
  US 20070234136A1
• Time in Patent Office: 1,075 Days
• Field of Search: 714/712, 714/715, 714/819, 714/746, 714/748, 714/760, 714/776, 714/799, 714/48, 714/43, 714/39, 714/807, 714/704
• US Class Current: 714/807
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/16 in which the return channel carries supervisory signals, e.g. repetition request signals
• CPC Class Codes: H04L 2001/0094 Bus

Abstract

A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.

Claims

1. In a storage processor of a data storage system, a method for detecting a transmission error for data transferred over an I2C bus between the storage processor and a controller of the data storage system during a data read procedure, comprising:

transmitting a data request signal to the controller over the I2C bus to request data from the controller;

receiving a data response signal from the controller over the I2C bus in response to the data request signal;

performing an error detection procedure on the data response signal to form a validation result;

comparing the validation result with a validation threshold; and

detecting (i) that the data response signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a first comparison result and (ii) that the data reply signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a second comparison result.

2. The method of claim 1, wherein:

receiving comprises receiving the data response signal from the controller over the I2C bus in response to the data request signal the data response signal including a data signal, a register address reply signal, and a checksum signal; and

performing the error detection procedure comprises;

summing the data signal, the register address reply signal, and the checksum signal to form a summation result; and

performing a modular division between the summation result and a denominator value to form the validation result.

3. The method of claim 2 wherein:

comparing the validation result comprises comparing the validation result with validation threshold, the validation threshold having a value of zero; and

detecting comprises detecting (i) that the data response signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result equal to the validation threshold and (ii) that the data reply signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result not equal to the validation threshold.

4. The method of claim 2, wherein:

transmitting comprises transmitting the data request signal to the controller over the I2C bus to request data from the controller, the data signal including a register address request signal that indicates the register to which the storage processor is writing;

performing further comprises comparing the register address request signal to the register address reply signal;

and detecting further comprises detecting (i) that the data response signal does not include errors caused by the I2C bus in the case where the register address request signal is equal to the register address reply signal and (ii) that the data reply signal does include errors caused by the I2C bus in the case where the register address request signal is not equal to the register address reply signal.

5. The method of claim 1, comprising:

in response to transmitting the data request signal, receiving the data response signal from the controller over the I2C bus, the data response signal including a placeholder signal as the data signal and a busy condition signal in place of the register address reply signal, the placeholder signal indicating a busy state of the controller; and

retransmitting the data request signal.

6. The storage processor of claim 5, wherein the storage processor is configured to:

in response to transmitting the data request signal, receive the data response signal from the controller over the I2C bus, the data response signal including a placeholder signal as the data signal and a busy condition signal in place of the register address reply signal, the placeholder signal indicating a busy state of the controller; and

retransmit the data request signal.

7. A storage processor of a data storage system having a controller and I2C bus configured to provide communication between the storage processor and the controller, the storage processor configured to

transmit a data request signal to the controller over the I2C bus to request data from the controller;

receive a data response signal from the controller over the I2C bus in response to the data request signal;

perform an error detection procedure on the data response signal to form a validation result;

compare the validation result with a validation threshold; and

detect (i) that the data response signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a first comparison result and (ii) that the data reply signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a second comparison result.

8. The storage processor of claim 7, wherein the storage processor is configured to:

when receiving, receive the data response signal from the controller over the I2C bus in response to the data request signal the data response signal including a data signal, a register address reply signal, and a checksum signal; and

when performing the error detection procedure;

sum the data signal, the register address reply signal, and the checksum signal to form a summation result; and

perform a modular division between the summation result and a denominator value to form the validation result.

9. The storage processor of claim 8, wherein the storage processor is configured to:

when comparing the validation result, compare the validation result with validation threshold, the validation threshold having a value of zero; and

when detecting, detect (i) that the data response signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result equal to the validation threshold and (ii) that the data reply signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result not equal to the validation threshold.

10. The storage processor of claim 8, wherein the storage processor is configured to:

when transmitting, transmit the data request signal to the controller over the I2C bus to request data from the controller, the data signal including a register address request signal that indicates the register to which the storage processor is writing;

when performing, further compare the register address request signal to the register address reply signal; and

when detecting, further detect (i) that the data response signal does not include errors caused by the I2C bus in the case where the register address request signal is equal to the register address reply signal and (ii) that the data reply signal does include errors caused by the I2C bus in the case where the register address request signal is not equal to the register address reply signal.

11. In a controller of a data storage system, a method for detecting a transmission error for data transferred over an I2C bus between the controller and a storage processor of the data storage system during a data write procedure, comprising:

receiving a data transmission signal from the storage processor over the I2C bus, the data transmission signal initiating writing of data to the controller;

performing an error detection procedure on the data transmission signal to form a validation result;

comparing the validation result with a validation threshold; and

detecting (i) that the data transmission signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a first comparison result and (ii) that the data transmission signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a second comparison result.

12. The method of claim 11, wherein:

receiving comprises receiving the data transmission signal from the storage processor over the I2C bus, the data transmission signal including a data signal, a register address request signal, and a checksum signal; and

performing the error detection procedure comprises;

summing the data signal, the register address request signal, and the checksum signal to form a summation result; and

performing a modular division between the summation result and a denominator value to form the validation result.

13. The method of claim 12 wherein:

comparing the validation result comprises comparing the validation result with validation threshold, the validation threshold having a value of zero; and

detecting comprises detecting (i) that the data transmission signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result equal to the validation threshold and (ii) that the data transmission signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result not equal to the validation threshold.

14. The method of claim 12, wherein receiving comprises receiving the data transmission signal from the storage processor over the I2C bus, the data transmission signal including a configuration characteristic signal, a register address request signal, and a checksum signal;

and

in response to detecting that the configuration characteristic signal does not include errors caused by the I2C bus, configuring a switch coupled to the controller to provide communication pathways between a first set of ports associated with the controller and a second set of ports associated with the storage processor based upon the configuration characteristic signal.

15. A controller of a data storage system having a storage processor and I2C bus configured to provide communication between the controller and the storage processor, the controller configured to:

receive a data transmission signal from the storage processor over the I2C bus, the data transmission signal initiating writing of data to the controller;

perform an error detection procedure on the data transmission signal to form a validation result;

compare the validation result with a validation threshold; and

detect (i) that the data transmission signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a first comparison result and (ii) that the data transmission signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a second comparison result.

16. The controller of claim 15, wherein:

when receiving, the controller is configured to receive the data transmission signal from the storage processor over the I2C bus the data response signal including a data signal, a register address request signal, and a checksum signal; and

when performing the error detection procedure, the controller is configured to;

sum the data signal, the register address request signal, and the checksum signal to form a summation result; and

perform a modular division between the summation result and a denominator value to form the validation result.

17. The controller of claim 16, wherein:

when comparing the validation result, the controller is configured to compare the validation result with validation threshold, the validation threshold having a value of zero; and

when detecting, the controller is configured to detect (i) that the data transmission signal does not include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result equal to the validation threshold and (ii) that the data transmission signal does include errors caused by the I2C bus in the case where the comparison between the validation result and the validation threshold produces a comparison result not equal to the validation threshold.

18. The controller of claim 16, wherein when receiving, the controller is configured to receive the data transmission signal from the storage processor over the I2C bus the data transmission signal including a configuration characteristic signal, a register address request signal, and a checksum signal;

and

in response to detecting that the configuration characteristic signal does not include errors caused by the I2C bus, the controller is configured to configure a switch coupled to the controller to provide communication pathways between a first set of ports associated with the controller and a second set of ports associated with the storage processor based upon the configuration characteristic signal.