Process of forming a non-volatile memory cell including a capacitor structure

• US 7,504,302 B2
• Filed: 03/18/2005
• Issued: 03/17/2009
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mathew, Leo, Stephens, Tab A., Muralidhar, Ramachandran
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US11/083,878
• Publication Number:
  US 20060220102A1
• Time in Patent Office: 1,460 Days
• Field of Search: 438/257, 438/393
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.

Claims

1. A process of forming a non-volatile memory cell comprising:

forming an active region over a substrate;

forming a first layer over the active region, wherein the first layer comprises a charge storage layer;

forming a second layer over the first layer, wherein the second layer has a different composition compared to the first layer;

forming a first etch mask over the second layer, wherein exposed portions of the first and second layers overlie the active region and are not covered by the first etch mask;

etching part of the exposed portion of the second layer;

etching part of the exposed portion of the first layer to leave a residual portion including a floating gate electrode and first capacitor electrodes, wherein the floating gate electrode overlies the active region, and the first capacitor electrodes are adjacent to opposite sides of the floating gate electrode;

removing the first etch mask;

forming a dielectric layer over the residual portion of the first layer; and

forming a control gate electrode over the dielectric layer,

wherein, from a top view in a finished device, a combination of the floating gate electrode and first capacitor electrodes laterally surrounds all sides of the active region.

2. The process of claim 1, wherein a portion of the first layer covered by the first etch mask corresponds to the floating gate electrode for the non-volatile memory cell, and another portion of the first layer not covered by the first etch mask corresponds to the first capacitor electrodes.

3. The process of claim 1, wherein etching part of the exposed portion of the second layer forms a sidewall spacer lying adjacent to the first layer.

4. The process of claim 3, wherein after etching part of the exposed portion of the first layer, only portions of the first layer covered by the first etch mask and sidewall spacer lie within the non-volatile memory cell.

5. The process of claim 1, wherein etching part of the exposed portion of the first layer is performed such that the first capacitor electrodes include distal portions spaced away from the floating gate electrode, wherein uppermost surfaces of the distal portions lie at elevations lower than a lowermost surface of the active region.

6. The process of claim 1, further comprising forming second and third capacitor electrodes, wherein from a top view, the first capacitor electrodes lie between the second and third capacitor electrodes.

7. The process of claim 6, wherein forming die control gate electrode and forming the second and third capacitor electrodes comprise:

forming a third layer over the dielectric layer; and

etching the third layer to form the control gate electrode and the second and third capacitor electrodes.

8. The process of claim 6, wherein etching part of the exposed portion of the first layer is performed such that the floating gate electrode and the first capacitor electrodes are electrically connected to one another.

9. The process of claim 8, wherein forming the first layer, etching part of the exposed portion of the first layer, forming the dielectric layer, forming the control gate electrode, and forming the second and third capacitor electrodes are performed to form a capacitor structure including a first capacitor structure electrode and a second capacitor structure electrode, wherein the first capacitor structure electrode includes the floating gate electrode and the first capacitor electrodes, and the second electrode includes the control gate electrode and the second and third capacitor electrodes.

10. A process of forming a non-volatile memory cell comprising:

forming an insulating layer over a substrate;

forming an active region over the insulating layer, wherein sides of the active region and a portion of the insulating layer are substantially coterminous with each other;

forming a gate dielectric layer lying along the active region;

forming a first layer comprising polysilicon;

etching the first layer to define a first portion, a second portion, and a third portion, wherein;

the first portion of the first layer overlies the gate dielectric layer and a channel region within the active region;

the second portion of the first layer is spaced apart from the active region and insulating layer and lies adjacent to a first side of the first portion of the first layer;

the third portion of the first layer is spaced apart from the active region and insulating layer and lies adjacent to a second side of the first portion of the first layer that is opposite the first side of the first portion of the first layer; and

from a top view, a combination of the first, second, and third portions of the first layer laterally surrounds all sides of the active region;

forming an interlevel dielectric layer after forming the first layer;

forming a second layer including polysilicon after forming the interlevel dielectric layer; and

etching the second layer to define a first portion, a second portion, and a third portion, wherein;

the first portion of the second layer overlies the first portion of the first layer, the gate dielectric layer, and the channel region within the active region;

the second portion of the second layer lies along a first side of the first portion of the second layer;

the third portion of the second layer lies along a second side of the first portion of the second layer that is opposite the first side of the first portion of the second layer;

from a top view, a part of the second portion of the second layer lies between the active region and the second portion of the first layer;

from a top view, a part of the third portion of the second layer lies between the active region and the third portion of the first layer; and

from a top view, a combination of the first, second, and third portions of the second layer laterally surrounds all sides of the active region and laterally surrounds the second and third portions of the first layer.

11. The process of claim 10, wherein etching the first layer is performed such that, from a top view, a combination of the first, second, and third portions of the first layer laterally surrounds the active region.

12. The process of claim 10, wherein:

etching the first layer is performed such that a floating gate electrode includes the first portion of the first layer; and

etching the second layer is performed such that a control gate electrode includes the first portion of the second layer.

13. The process of claim 12, wherein:

etching the first layer is performed such that the first, second, and third portions of the first layer are electrically connected to one another; and

etching the second layer is performed such that the first, second, and third portions of the second layer are electrically connected to one another.

14. The process of claim 13, wherein forming the first layer, etching the first layer, forming the interlevel dielectric, forming the second layer, and etching the second layer are performed to form a capacitor structure including a first electrode and a second electrode, wherein the first electrode includes the first, second, and third portions of the first layer;

and the second electrode includes the first, second, and third portions of the second layer.

15. The process of claim 10, wherein etching the first layer is performed such that the second and third portions of the first layer lie at elevations lower than the active region.

16. A process of forming a non-volatile memory cell comprising:

forming an active region over a substrate;

forming a first layer over the active region, wherein the first layer comprises a charge storage layer;

forming a second layer over the first layer, wherein the second layer has a different composition compared to the first layer;

etching the second layer to form sidewall spacers;

forming a first etch mask over the first layer, wherein exposed portions of the first layer overlie the active region and are not covered by the first etch mask;

etching part of the exposed portion of the first layer to leave a residual portion including a floating gate electrode and first capacitor electrodes, wherein the first capacitor electrodes lie at elevations lower than the active region;

removing the first etch mask;

forming a dielectric layer over the residual portion of the first layer; and

forming a control gate electrode over the dielectric layer,

wherein in a finished device, the first capacitor electrodes extend from the opposite sides of the floating gate electrode in directions substantially parallel to a length of the active region.

17. The process of claim 16, further comprising forming second and third capacitor electrodes, wherein from a top view, the first capacitor electrodes lie between the second and third capacitor electrodes.

18. The process of claim 17, wherein:

forming the first layer and etching part of the exposed portion of the first layer is performed such that, from a top view, a combination of the floating gate electrode and the first capacitor electrodes laterally surrounds the active region; and

forming the control gate electrode and forming the second and third capacitor electrodes are performed such that, from a top view, a combination of the control gate electrode and the second and third capacitor electrodes laterally surrounds the active region.

19. The process of claim 17, wherein forming the control gate electrode and forming the second and third capacitor electrodes comprise:

forming a third layer over the dielectric layer; and

etching the third layer to form the control gate electrode and the second and third capacitor electrodes.

20. The process of claim 19, wherein:

etching part of the exposed portion of the first layer is performed such that the floating gate electrode and the first capacitor electrodes are electrically connected to one another; and

forming the control gate electrode and forming the second and third capacitor electrodes is performed such that the control gate electrode and the second and third capacitor electrodes are electrically connected to one another.