Integrated circuit having bond pad with improved thermal and mechanical properties

• US 7,504,728 B2
• Filed: 12/09/2005
• Issued: 03/17/2009
• Est. Priority Date: 12/09/2005
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Ryan, Vivian
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/298,030
• Publication Number:
  US 20070134903A1
• Time in Patent Office: 1,194 Days
• Field of Search: 257764-762, 257786-785, 257/E21.519, 257/E23.02, 438612-618
• US Class Current: 257/764
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48471 : the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85201 : Compression bonding
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The metallization layer is in electrical contact with at least a portion of the active circuitry. In addition, the capping layer is formed over at least a portion of the metallization layer and is in electrical contact with the metallization layer. The grooves in the capping layer may be located only proximate to the edges of the bond pad or may run throughout the bond pad depending on the application.

Claims

1. An integrated circuit including active circuitry and at least one bond pad, the at least one bond pad comprising:

a metallization layer, the metallization layer in electrical contact with at least a portion of the active circuitry; and

a capping layer, the capping layer formed over at least a portion of the metallization layer and in electrical contact with the metallization layer;

wherein the capping layer is patterned to comprise a plurality of etched grooves;

wherein one or more of said etched grooves are formed in an upper surface of the capping layer but do not extend through the capping layer to a lower surface of the capping layer;

at least one of said etched grooves thereby having a depth which is less than a thickness of the capping layer between said upper and lower surfaces.

2. The integrated circuit of claim 1, wherein the metallization layer comprises copper.

3. The integrated circuit of claim 1, wherein the capping layer comprises aluminum.

4. The integrated circuit of claim 1, further comprising a passivation layer, the passivation layer defining an opening over the metallization layer through which the capping layer electrically contacts the metallization layer.

5. The integrated circuit of claim 1, wherein the capping layer has a thickness between about 500 and 2,500 nanometers.

6. The integrated circuit of claim 1, wherein at least one of the etched grooves in the capping layer has a width between about 350 and 1,500 nanometers.

7. The integrated circuit of claim 1, wherein the depth of at least one of the etched grooves in the capping layer is about 40 to 60% of the thickness of the capping layer.

8. The integrated circuit of claim 1, wherein the capping layer comprises a plurality of etched grooves that run parallel relative to one another.

9. The integrated circuit of claim 1, wherein the capping layer in the plane parallel to a surface of the capping layer is substantially square or substantially rectangular.

10. The integrated circuit of claim 1, wherein at least one of the etched grooves in the capping layer is located substantially proximate to one or more corners of the capping layer.

11. The integrated circuit of claim 1, wherein at least one of the etched grooves in the capping layer runs substantially perpendicular to one or more edges of the capping layer.

12. The integrated circuit of claim 1, wherein at least one of the etched grooves in the capping layer runs substantially at a 45 degree angle relative to one or more edges of the capping layer.

13. The integrated circuit of claim 1, wherein the bond pad further comprises a barrier layer, the barrier layer lying between the metallization layer and the capping layer.

14. The integrated circuit of claim 13, wherein the barrier layer comprises tantalum.

15. The integrated circuit of claim 1, wherein at least one of the one or more bond pads is an extended bond pad.

16. An integrated circuit including active circuitry and at least one bond pad, the at least one bond pad comprising:

a metallization layer, the metallization layer in electrical contact with at least a portion of the active circuitry;

a capping layer, the capping layer formed over at least a portion of the metallization layer and in electrical contact with the metallization layer; and

a passivation layer, the passivation layer defining an opening over the metallization layer through which the capping layer electrically contacts the metallization layer;

wherein the capping layer is patterned to comprise a plurality of etched grooves; and

wherein the capping layer lies at least partially on top of the passivation layer.

17. An integrated circuit mounted in an integrated circuit package, the integrated circuit including active circuitry and a bond pad, wherein the bond pad comprises:

a metallization layer, the metallization layer in electrical contact with at least a portion of the active circuitry; and

a capping layer, the capping layer formed over at least a portion of the metallization layer and in electrical contact with the metallization layer;

wherein the capping layer is patterned to comprise a plurality of etched grooves;

wherein one or more of said etched grooves are formed in an upper surface of the capping layer but do not extend through the capping layer to a lower surface of the capping layer;

at least one of said etched grooves thereby having a depth which is less than a thickness of the capping layer between said upper and lower surfaces.

18. The integrated circuit of claim 17, wherein the integrated circuit package is electrically coupled to the integrated circuit using wire bonding technology.

19. The integrated circuit of claim 17, wherein the integrated circuit package is electrically coupled to the integrated circuit using flip chip bonding technology.

20. A method of forming a bond pad in an integrated circuit including active circuitry, the method comprising the steps of:

forming a metallization layer, the metallization layer in electrical contact with at least a portion of the active circuitry; and

forming a capping layer over at least a portion of the metallization layer and in electrical contact with the metallization layer;

wherein the capping layer is patterned to comprise a plurality of etched grooves;

wherein one or more of said etched grooves are formed in an upper surface of the capping layer but do not extend through the capping layer to a lower surface of the capping laver;

at least one of said etched grooves thereby having a depth which is less than a thickness of the capping layer between said upper and lower surfaces.