Three dimensional structure memory
DC CAFCFirst Claim
Patent Images
1. A stacked integrated circuit comprising:
- a first thinned substantially flexible integrated circuit layer having a bottom-side surface;
a second thinned substantially flexible integrated circuit layer having a top-side surface, wherein the first integrated circuit layer overlies the second integrated circuit layer such that the bottom-side surface overlies at least part of the top-side surface, and wherein at least one of the first and second thinned substantially flexible integrated circuit layers comprises a low stress dielectric layer; and
an inter-layer stacked between the bottom-side surface of the first integrated circuit layer and the top-side surface of the second integrated circuit layer, wherein the inter-layer includes at least a first inter-layer portion and a second inter-layer portion that is electrically isolated from at least the first inter-layer portion, wherein each one of the first and second inter-layer portions forms a bond between the bottom-side surface of the first integrated circuit layer and the top-side surface of the second integrated circuit layer, and wherein only one of the first and second inter-layer portions forms at least one interconnection electrically coupling the first integrated circuit layer to the second integrated circuit layer for the transfer of information, wherein the at least one interconnection between the first and second integrated circuit layers is formed only on the bottom-side and top-side surfaces.
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Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
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Citations
68 Claims
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1. A stacked integrated circuit comprising:
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a first thinned substantially flexible integrated circuit layer having a bottom-side surface; a second thinned substantially flexible integrated circuit layer having a top-side surface, wherein the first integrated circuit layer overlies the second integrated circuit layer such that the bottom-side surface overlies at least part of the top-side surface, and wherein at least one of the first and second thinned substantially flexible integrated circuit layers comprises a low stress dielectric layer; and an inter-layer stacked between the bottom-side surface of the first integrated circuit layer and the top-side surface of the second integrated circuit layer, wherein the inter-layer includes at least a first inter-layer portion and a second inter-layer portion that is electrically isolated from at least the first inter-layer portion, wherein each one of the first and second inter-layer portions forms a bond between the bottom-side surface of the first integrated circuit layer and the top-side surface of the second integrated circuit layer, and wherein only one of the first and second inter-layer portions forms at least one interconnection electrically coupling the first integrated circuit layer to the second integrated circuit layer for the transfer of information, wherein the at least one interconnection between the first and second integrated circuit layers is formed only on the bottom-side and top-side surfaces. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A stacked integrated circuit comprising:
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a first thinned substantially flexible substrate having circuitry and a bottom-side surface; a second thinned substantially flexible substrate having circuitry and a top-side surface, wherein the first thinned substantially flexible substrate overlies the second thinned substantially flexible substrate, such that the bottom-side surface overlies at least part of said top-side surface; and an inter-layer stacked between the bottom-side surface of the first thinned substantially flexible substrate and the top-side surface of the second thinned substantially flexible substrate, wherein the inter-layer includes at least a first inter-layer portion and a second inter-layer portion that is electrically isolated from at least the first inter-layer portion, wherein each one of the first and second inter-layer portions forms a bond between the bottom-side surface of the first thinned substantially flexible substrate and the top-side surface of the second thinned substantially flexible substrate, and wherein only one of the first and second inter-layer portions forms at least one interconnection electrically coupling the circuitry on the first substantially flexible substrate and the circuitry on the second substantially flexible substrate. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A stacked integrated circuit, comprising:
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a first thinned substantially flexible substrate having circuitry and a first facing surface; a second thinned substantially flexible substrate having circuitry and a second facing surface, wherein the first thinned substantially flexible substrate overlies the second thinned substantially flexible substrate, such that a region of the first facing surface overlies and faces the second facing surface; and an inter-layer between the region of the first facing surface and the second facing surface, wherein the inter-layer includes at least a first inter-layer portion and a second inter-layer portion, wherein each one of the first and second inter-layer portions forms a bond between the region of the first facing surface and the second facing surface, and wherein only one of the first and second inter-layer portions forms at least one conductive path between the circuitry of the first thinned substantially flexible substrate and the circuitry of the second thinned substantially flexible substrate. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A stacked integrated circuit, comprising:
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a first substrate having circuitry formed thereon and a first facing surface; a second substrate having circuitry thereon and a second facing surface, wherein the second substrate overlies the first substrate, such that a region of the second facing surface overlies and faces a region of the first facing surface; and an inter-layer between the region of the first facing surface and the region of the second facing surface, wherein the inter-layer includes at least a first inter-layer portion and a second inter-layer portion, wherein each one of the first and second inter-layer portions forms a bond between the region of the first facing surface and the region of the second facing surface, and wherein only one of the first and second inter-layer portions forms at least one conductive path between the circuitry of the first substrate and the circuitry of the second substrate. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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Specification