Automatically balanced sensing device and method for multiple capacitive sensors

• US 7,504,833 B1
• Filed: 03/31/2006
• Issued: 03/17/2009
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Seguine, Dennis
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): ZHU, JOHN X
• Application Number:
  US11/395,417
• Time in Patent Office: 1,082 Days
• Field of Search: 324/669, 324/665, 324/672, 382/124
• US Class Current: 324/672
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing

Abstract

Disclosed is method for compensating for variation in the capacitance between multiple capacitive sensors. Prior to sensing operations, baseline capacitance values can be acquired for all sensors. A correction factor can be calculated based on such baseline values. During sensing operations (run-time), variations in capacitance from baseline values can be modified by appropriate correction factors. Sensitivity between sensors can thus be made more uniform.

Claims

1. A circuit, comprising:

a plurality of input switches, each enabling or disabling a low impedance from a corresponding capacitance source to a common node, each capacitance source having an essentially constant value in an initial mode and subject to potential variation in a run-time mode;

a common current source coupled to the common node; and

a comparator circuit having a first input coupled to the common node and a second input coupled to a reference value that compares capacitance values corresponding to each capacitance source to the reference value in the initial mode and subsequently compares capacitance values corresponding to each capacitance source to the reference value in the run-time mode.

2. The circuit of claim 1, further including:

the comparator has an output; and

a common node set switch coupled between the common node and a predetermined voltage node that is enabled in response to the output of the comparator.

3. The circuit of claim 2, wherein:

the common current source is coupled between a high power supply node and the common node; and

the common node set switch is coupled between the common node and a low power supply node.

4. The circuit of claim 1, further including:

a counter circuit coupled to an output of the comparator that generates a count value corresponding to each capacitance source based on transitions in the output of the comparator circuit.

5. The circuit of claim 4, further including:

the counter circuit generating count values corresponding to each capacitance source in the initial mode; and

a computation circuit that generates at least one correction factor from at least one of the initial mode count values that compensates for differences between the count values of different capacitance sources generated in the initial mode.

6. The circuit of claim 5, wherein:

the correction factor is generated from a maximum count value of all the count values of the initial mode.

7. The circuit of claim 6, wherein:

the computation circuit generates a correction factor corresponding to each capacitance source, each correction factor including a maximum count value taken from all the count values of the initial mode divided by the count value for the capacitance source.

8. The circuit of claim 5, wherein:

the correction factor is generated from a minimum count value of all the count values of the initial mode.

9. The circuit of claim 5, wherein:

the correction factor is generated from an average count value from all count values of the initial mode.

10. A circuit, comprising:

a plurality of input switches, each having a signal path coupled between a corresponding capacitance source to a common node, each input switch being controlled by a different input control signal and each capacitance source having an essentially constant value in an initial mode and subject to potential variation in a run-time mode;

a common current source coupled to the common node; and

a comparator circuit having a first input coupled to the common node and a second input coupled to a reference value that compares capacitance values corresponding to each capacitance source to the reference value in the initial mode and subsequently compares capacitance values corresponding to each capacitance source to the reference value in the run-time mode.