Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit

• US 7,504,850 B2
• Filed: 08/03/2006
• Issued: 03/17/2009
• Est. Priority Date: 02/04/2004
• Status: Expired due to Fees

• Current Assignee: Japan Aerospace Exploration Agency
• Original Assignee: High-Reliability Engineering & Components Corporation, Japan Aerospace Exploration Agency
• Inventors: Shindou, Hiroyuki, Makihara, Akiko, Kuboyama, Satoshi, Iide, Yoshiya
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/499,498
• Publication Number:
  US 20070069305A1
• Time in Patent Office: 957 Days
• Field of Search: 326 9- 10, 326 12- 15
• US Class Current: 326/9
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits

Abstract

Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

Claims

1. A single-event-effect tolerant SOI-based inverter comprising a first p-channel MOS transistor and a first n-channel MOS transistor, which are formed on a substrate having an SOI structure to provide a floating body structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, wherein:

each of said first p-channel MOS transistor and said first n-channel MOS transistor is combined with a second MOS transistor having a channel of a same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that they are connected in series with respect to the source or drain line, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistors are connected together via a short line, so as to formed a double structure.

3. A single-event-effect tolerant SOI-based semiconductor memory device which is formed on a substrate having an SOI structure to provide a floating body structure and including two inverters, said inverters having respective outputs cross-connected to respective inputs thereof directly or indirectly through a switching gate, wherein at least one of said inverters consists of the single-event-effect tolerant SOI-based inverter as defined in claim 1 or 2.

4. A single-event-effect tolerant SOI-based data latch circuit which is formed on a substrate having an SOI structure to provide a floating body structure and including a first inverter, a second inverter and a clocked inverter, wherein:

said first inverter has an output connected to an input of said second inverter;

said second inverter has an output connected to an input of said first inverter through a connection to be subject to on-off control based on first complementary clock signals having logic values complementary to each other; and

said clocked inverter is operable to invert an received input and output said inverted input to the input of said first inverter under on-off control based on second complementary clock signals opposite in phase relative to said first complementary clock signals,

wherein at least one of said first and second inverters consists of the single-event-effect tolerant SOI-based inverter as defined in claim 1 or 2.

5. The data latch circuit as defined in claim 4, wherein said clocked inverter includes a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor and a third n-channel MOS transistor, which are connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of the first voltage source to a node connected to the side of the second voltage source, wherein:

said second complementary clock signals are applied, respectively, to a first gate group consisting of respective gates of said first and third p-channel MOS transistors, and a second gate group consisting of said first and third n-channel MOS transistors;

each of said second p-channel MOS transistor and said second n-channel MOS transistor serves as an input section of said data latch circuit; and

a node between said third p-channel MOS transistor and said first n-channel MOS transistor serves as an output section of said clocked inverter.

2. A single-event-effect tolerant SOI-based inverter comprising:

a first p-channel MOS transistor, a second p-channel MOS transistor, a first n-channel MOS transistor and a second n-channel MOS transistor, which are formed on a substrate having an SOI structure to provide a floating body structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, wherein;

said first p-channel MOS transistor, said second p-channel MOS transistor, said first n-channel MOS transistor and said second n-channel MOS transistor are arranged to form an inverter circuit;

respective gates of said first p-channel MOS transistor, said second p-channel MOS transistor, said first n-channel MOS transistor and said second n-channel MOS transistors are connected to a common node so as to be connected to an input of said inverter circuit, and

respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistor are connected together via a short line,

whereby said first and second p-channel MOS transistors are formed as a double-structured p-channel MOS transistor, and said first and second n-channel MOS transistors are formed as a double-structured n-channel MOS transistor.

6. A single-event-effect tolerant SOI-based 2-input NAND element comprising:

a pair of a first p-channel MOS transistor and a second p-channel MOS transistor which have channels connected in parallel with each other; and

a pair of a first n-channel MOS transistor and a second n-channel MOS transistor which have channels connected in series with each other, wherein;

said p-channel MOS transistor pair and said n-channel MOS transistor pair are formed on a substrate having an SOI structure to provide a floating body structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;

respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;

respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input; and

a node between said p-channel MOS transistor pair and said n-channel MOS transistor pair is connected to an output,

wherein each of said first p-channel MOS transistor, said second p-channel MOS transistor, said first n-channel MOS transistor and said second n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure.

7. The single-event-effect tolerant SOI-based 2-input NAND element as defined in claim 6, wherein said additional n-channel MOS transistors combined, respectively, with said first n-channel MOS transistor and said second n-channel MOS transistor through their series-connected channels for forming the double structure, are connected thereto except for a position between said first and second n-channel MOS transistors.

8. A single-event-effect tolerant SOI-based 3-input NAND element comprising:

a group of a first p-channel MOS transistor, a second p-channel MOS transistor and a third p-channel MOS transistor which have channels connected in parallel with each other; and

a group of a first n-channel MOS transistor a second n-channel MOS transistor and a third n-channel MOS transistor which have channels connected in series with each other, wherein;

said p-channel MOS transistor group and said n-channel MOS transistor group are formed on a substrate having an SOI structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;

respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;

respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input;

respective gates of said third p-channel MOS transistor and said third n-channel MOS transistor are connected to a third input; and

a node between said p-channel MOS transistor group and said n-channel MOS transistor group is connected to an output,

wherein each of said first p-channel MOS transistor, said second p-channel MOS transistor, said third p-channel MOS transistor, said first n-channel MOS transistor, said second n-channel MOS transistor and said third n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure.

9. The single-event-effect tolerant SOI-based 3-input NAND element as defined in claim 8, wherein said additional n-channel MOS transistors combined, respectively, with said first n-channel MOS transistor, said second n-channel MOS transistor and said third n-channel MOS transistor through their series-connected channels for forming the double structure, are connected thereto except for a position between any two of said first, second and third n-channel MOS transistors.

10. A single-event-effect tolerant SOI-based 2-input NOR element comprising:

a pair of a first p-channel MOS transistor and a second p-channel MOS transistor which have channels connected in series with each other; and

a pair of a first n-channel MOS transistor and a second n-channel MOS transistor which have channels connected in parallel with each other, wherein;

said p-channel MOS transistor pair and said n-channel MOS transistor pair are formed on a substrate having an 501 structure to provide a floating body structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;

respective gates of said first p-channel MOS transistor and said first n-channel MOS transistor are connected to a first input;

respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input; and

a node between said p-channel MOS transistor pair and said n-channel MOS transistor pair is connected to an output,

wherein each of the first p-channel MOS transistor, the second p-channel MOS transistor, the first n-channel MOS transistor and the second n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure.

11. The single-event-effect tolerant SOI-based 2-input NOR element as defined in claim 10, wherein said additional p-channel MOS transistors combined, respectively, with said first p-channel MOS transistor and said second p-channel MOS transistor through their series-connected channels for forming the double structure, are connected thereto except for a position between said first and second p-channel MOS transistors.

12. A single-event-effect tolerant SOI-based 3-input NOR element comprising:

a group of a first p-channel MOS transistor, a second p-channel MOS transistor and a third p-channel MOS transistor which have channels connected in series with each other; and

a group of a first n-channel MOS transistor, a second n-channel MOS transistor and a third n-channel MOS transistor which have channels connected in parallel with each other, wherein;

said p-channel MOS transistor group and said n-channel MOS transistor group are formed on a substrate having an 501 structure to provide a floating body structure, and connected in series in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source;

respective gates of said first p-channel MOS transistor and said first n-channel channel MOS transistor are connected to a first input;

respective gates of said second p-channel MOS transistor and said second n-channel MOS transistor are connected to a second input;

respective gates of said third p-channel MOS transistor and said third n-channel MOS transistor are connected to a third input; and

a node between said p-channel MOS transistor group and said n-channel MOS transistor group is connected to an output,

wherein each of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor and the third n-channel MOS transistor, is combined with an additional MOS transistor having a channel of the same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that their channels are connected in series, so as to form a double structure.

13. The single-event-effect tolerant SOI-based 3-input NOR element as defined in claim 12, wherein said additional p-channel MOS transistors combined, respectively, with said first p-channel MOS transistor, said second p-channel MOS transistor and said third p-channel MOS transistor through their series-connected channels for forming the double structure, are connected thereto except for a position between any two of said first, second and third p-channel channel MOS transistors.

14. A single-event-effect tolerant SOI-based data latch circuit which is formed on a substrate having an SOI structure and including a first inverter, a second inverter and a clocked inverter, wherein:

said first inverter has an output connected to an input of said second inverter;

said second inverter has an output connected to an input of said first inverter; and

said clocked inverter is operable to invert an received input and output said inverted input to the input of said first inverter under on-off control based on first complementary clock signals having logic values complementary to each other, wherein at least one of said first and second inverters is a single-event-effect tolerant SOI-based inverter comprising a first p-channel MOS transistor and a first n-channel MOS transistor, which are formed on a substrate having an SOI structure, and connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source, each of said first p-channel MOS transistor and said first n-channel MOS transistor being combined with a second MOS transistor having a channel of a same conductive type as that thereof and a gate interconnected to a gate thereof, in such a manner that they are connected in series with respect to the source or drain line, and respective nodes between said first and second p-channel MOS transistors and between said first and second n-channel MOS transistors are connected together, so as to formed a double structure, and

at least one of said first and second inverters is a clocked inverter subject to on-off control based on second complementary clock signals opposite in phase relative to said first complementary clock signals.