Configurable integrated circuit with parallel non-neighboring offset connections

• US 7,504,858 B1
• Filed: 03/08/2006
• Issued: 03/17/2009
• Est. Priority Date: 03/08/2006
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Hutchings, Brad, Schmit, Herman
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Tabler, Matthew C
• Application Number:
  US11/371,191
• Time in Patent Office: 1,105 Days
• Field of Search: 326 38- 41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some aspects of the present invention involve connections in a configurable IC. Some embodiments provide a configurable integrated circuit with a first array of tiles. The first array of tiles has columns and rows of tiles. The IC has a first tile within the first array of tiles. The first tile has a set of outputs. The IC has a second tile in the array of tiles. The second tile has a set of inputs. The IC has a non-neighboring offset connection (NNOC) from an output of the first tile to an input of the second tile. The second tile is offset from the first tile by at least one row and at least two columns or by at least two rows and at least one column.

Claims

1. A configurable integrated circuit (IC) comprising:

a) a first array of tiles, wherein said first array of tiles comprises columns and rows of tiles;

b) a first plurality of tiles within said first array of tiles, wherein each tile of said first plurality of tiles comprises a set of outputs;

c) a second plurality of files within said first array of tiles, wherein each tile of said second plurality of tiles comprises a set of inputs; and

d) a plurality of non-neighboring offset connections (NNOCs), wherein each NNOC of said plurality of NNOCs connects an output of a tile of said first plurality of tiles to an input of a non-neighboring offset tile of said second plurality of tiles, wherein a first particular tile is a non-neighboring offset tile of a second particular tile when said particular second tile is offset from said first particular tile by at least one row and at least two columns or by at least two rows and at least one column, wherein said NNOCs serve as a configurable data bus when a configurable resource in each of said non-neighboring offset tiles of said second plurality of tiles is configured to examine a signal supplied by the NNOC connected to said input of the non-neighboring offset tile of said second plurality of tiles, wherein each NNOC of said plurality of NNOCs is topologically parallel to each other NNOC within said plurality of NNOCs.

2. The configurable IC of claim 1, wherein said output of each tile within said first plurality of tiles is a corresponding output of an output of each other tile within said first plurality of tiles.

3. The configurable IC of claim 2, wherein said input of each tile within said second plurality of tiles is a corresponding input of an input of each other tile within said second set of tiles.

4. The configurable IC of claim 1, further comprising a second array of tiles, wherein said second array of tiles is a topological representation of said first array of tiles.

16. The configurable IC of claim 1, wherein a first particular NNOC is topologically parallel to a second particular NNOC when the first particular NNOC connects a first pair of two tiles with a relative offset from each other and the second particular NNOC connects a second pair of tiles with the same relative offset from each other.

17. The configurable IC of claim 1, wherein a first particular NNOC is topologically parallel to a second particular NNOC when the first particular NNOC connects a first pair of two tiles with a relative offset from each other and the second particular NNOC connects a second pair of tiles with a topologically similar relative offset from each other.

18. The configurable integrated circuit (IC) of claim 1, wherein each tile of said plurality of tiles comprises:

a) a logic circuit;

b) a set of input select interconnects, wherein the set of input select interconnects provides its output only to the logic circuit; and

c) a set of routing interconnects.

19. The configurable IC of claim 18, wherein a routing interconnect of the set of routing interconnects provides its output directly to said set of input select interconnects.

20. The configurable IC of claim 18, wherein a routing interconnect of the set of routing interconnects provides its output directly to a set of routing interconnects on other tiles.

21. The configurable IC of claim 18, wherein an input select interconnect of said set of input select interconnects receives output directly from a routing interconnect on another tile.

22. The configurable IC of claim 18, wherein an input select interconnect of said set of input select interconnects receives output directly from a logic circuit on another tile.

23. The configurable IC of claim 18, wherein a routing interconnect of said set of input select interconnects receives output directly from a routing interconnect on another tile.

24. The configurable IC of claim 18, wherein a routing interconnect of said set of routing interconnects receives output directly from a logic circuit on another tile.

37. The configurable IC of claim 1, wherein each NNOC of said plurality of NNOCs comprises an intervening buffer circuit.

38. The configurable IC of claim 1, wherein a first particular tile is a non-neighboring offset tile of a second particular tile when said particular second tile is offset from said first particular tile by at least one row and at least three columns or by at least three rows and at least one column.

5. A method of designating connections in designing a configurable integrated circuit (IC), said method comprising:

a) generating a plan for an array of tiles;

b) designating a plurality of non-neighboring offset connections (NNOCs) that each connect two tiles in the array that are not neighbors to each other and are not aligned with each other horizontally or vertically in the array connecting a first plurality of tiles in said array to a second plurality of tiles in said array, wherein;

i) a first NNOC of said plurality of NNOCs connects a first tile of said first plurality of tiles to a first tile of said second plurality of tiles,

ii) a second NNOC of said plurality of NNOCs connects a second tile of said first plurality of tiles to a second tile of said second plurality of tiles, and

iii) the first tile of said first plurality of tiles is offset from said first tile of said second plurality of tiles in the same way that the second tile of the first plurality of tiles is offset from the second tile of the first plurality of tiles; and

c) rearranging the positions of the tiles in the array while maintaining the designated NNOCs.

25. The method of claim 5, wherein rearranging the positions of the tiles in the array causes a pair of tiles, connected by an NNOC, that was not aligned vertically or horizontally to become aligned vertically or horizontally.

26. The method of claim 25, wherein the alignment of the pair of tiles causes the NNOC connecting the pair of tiles to become a non-neighboring, non-offset connector.

6. A method of designating connections in designing a configurable integrated circuit (IC), said method comprising:

a) selecting a first plurality of tiles in an array of tiles;

b) selecting a second plurality of tiles in said array of tiles;

c) planning a first non-neighboring offset connection from a first tile in said first plurality of tiles to a first tile in said second plurality of tiles; and

d) planning a second non-neighboring offset connection from a second tile in said first plurality of tiles to a second tile in said second plurality of tiles wherein said first non-neighboring offset connection is topologically parallel to said second non-neighboring offset connection, and wherein said first and second non-neighboring offset connections comprise two bit-lines of a first configurable data bus.

7. The method of claim 6, further comprising:

a) selecting a third plurality of tiles in said array of tiles; and

b) planning a third non-neighboring offset connection from a first tile in said third plurality of tiles to said first tile in said second plurality of tiles, wherein said third non-neighboring offset connection is a first bit line of a second configurable data bus.

8. The method of claim 7, further comprising planning a fourth non-neighboring offset connection from a second tile in said third plurality of tiles to said second tile in said second plurality of tiles, wherein said fourth non-neighboring offset connection is a second bit line of said second configurable data bus.

9. The method of claim 6, further comprising:

a) selecting a third plurality of tiles in said array of tiles; and

b) planning a third non-neighboring offset connection from a first tile in said third plurality of tiles to said first tile in said first plurality of tiles, wherein said third non-neighboring offset connection is a first bit line of a second configurable data bus.

10. The method of claim 9, further comprising planning a fourth non-neighboring offset connection from a second tile in said third plurality of tiles to said second tile in said first plurality of tiles, wherein said fourth non-neighboring offset connection is a second bit line of a second configurable data bus.

11. The method of claim 6, wherein the first plurality of tiles is all within a first pair of adjacent rows of tiles.

12. The method of claim 11, wherein the second plurality of tiles is all within a second pair of adjacent rows of tiles.

13. The method of claim 12, wherein the first pair of adjacent rows of tiles is at least three rows away from the second pair of adjacent rows of tiles.

14. The method of claim 6, wherein the first plurality of tiles is all within a first pair of adjacent columns.

15. The method of claim 14, wherein the second plurality of tiles is all within a second pair of adjacent columns.

27. The method of claim 6, wherein a first particular NNOC is topologically parallel to a second particular NNOC when the first particular NNOC connects a first pair of two tiles with a relative offset from each other and the second particular NNOC connects a second pair of files with the same relative offset from each other.

28. An integrated circuit (IC) comprising:

a) a plurality of tiles in an arrangement, wherein each tile of said plurality comprises an input;

b) a first set of tiles in said plurality;

c) a second set of tiles in said plurality, wherein each tile of said first set of tiles has a corresponding tile in said second set of tiles;

d) a first data bus entering said first set of tiles; and

e) a plurality of topologically parallel connections, wherein each of said plurality of topologically parallel connections connects a tile of said first set of tiles to a corresponding tile in said second set of tiles, wherein said topologically parallel connections are for implementing a second data bus that is active when a configurable resource of each tile of said second set of tiles is configured to accept data from said topologically parallel connections, wherein said second data bus is offset from said first data bus that enters said first set of tiles.

29. The IC of claim 28, wherein each corresponding tile in said second set of tiles is a non-neighboring offset tile to the corresponding tile in the first set of tiles.

30. The IC of claim 29, wherein a plurality of connections are physically parallel connections when they are designed to connect a plurality of pairs of tiles, wherein the tiles of each of said pairs of tiles is offset from each other by the same distance and in the same direction as the tiles in the other pairs of tiles, and wherein a plurality of connections are topologically parallel when connectivity of a set of physically parallel connections is maintained when the positions of the tiles are re-arranged during IC design.

31. The IC of claim 30, wherein the plurality of topologically parallel connections are not all physically parallel.

32. The IC of claim 30, wherein said first data bus enters said second set of tiles, connects at least some tiles of said first set of tiles to at least some tiles of said second set of tiles, but does not connect said corresponding tiles to each other.

33. For an integrated circuit comprising a plurality of configurable tiles arranged in a plurality of rows and columns, wherein said plurality comprises a first set of tiles and a second set of tiles, a method of creating a configurable data bus, said method comprising:

a) identifying a plurality of topologically parallel connections each of which connects a particular tile of the first set of tiles to a corresponding particular tile of the second set of tiles that is offset by at least one column and at least two rows or by at least two columns and at least one row from the particular tile of the first set of tiles; and

b) in order to configurably establish a data bus from the topologically parallel connections, defining configurations of configurable resources that receive the topologically parallel connections in the second set of tiles to examine signals received along the topologically parallel connections.

34. The method of claim 33, wherein each tile of said second set of tiles is offset from its corresponding tile of said first set of tiles by the same amount.

35. The method of claim 33, wherein each tile of said second set of tiles is connected to its corresponding tile of said first set of tiles by a connection that is topologically parallel to the non-neighboring offset connections connecting the other tiles of said second set of tiles to the corresponding tiles of the first set of tiles.

36. The method of claim 35, wherein a plurality of connections are physically parallel connections when they are designed to connect a plurality of pairs of tiles, wherein the tiles of each of said pairs of tiles is offset from each other by the same distance and in the same direction as the tiles in the other pairs of tiles, and wherein a plurality of connections are topologically parallel when connectivity of a set of physically parallel connections is maintained when the positions of the tiles are re-arranged during IC design.