Hybrid delta-sigma/SAR analog to digital converter and methods for using such

• US 7,504,977 B2
• Filed: 04/23/2007
• Issued: 03/17/2009
• Est. Priority Date: 04/23/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Doorenbos, Jerry L., Trifonov, Dimitar T., Gardner, Marco A.
• Primary Examiner(s): Nguyen; Linh V
• Application Number:
  US11/738,566
• Publication Number:
  US 20080258951A1
• Time in Patent Office: 694 Days
• Field of Search: 341/118, 341/120, 341/143, 341/155, 341/172
• US Class Current: 341/143
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/46 using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type

Abstract

Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.

Claims

1. An analog to digital converter, wherein the analog to digital converter includes a first stage and a second stage, wherein the first stage provides a first result and a residue, wherein the first stage operates as a delta-sigma based analog to digital converter, wherein the second stage receives the residue and provides a second result, wherein the second stage operates as a Successive Approximation Register based analog to digital converter, wherein the first stage includes an operational amplifier and a comparator, wherein an output of the operational amplifier is electrically coupled to an input of the comparator, and wherein the second stage reuses the same operational amplifier and comparator.

2. The analog to digital converter of claim 1, wherein the Successive Approximation Register based analog to digital converter produces a single bit of resolution for each Successive Approximation Register cycle.

3. The analog to digital converter of claim 2, wherein the Successive Approximation Register based analog to digital converter utilizes a window comparator.

4. The analog to digital converter of claim 1, wherein the Successive Approximation Register based analog to digital converter produces a single bit of resolution for each two Successive Approximation Register cycles.

5. The analog to digital converter of claim 4, wherein the Successive Approximation Register based analog to digital converter utilizes a single threshold comparator.

6. The analog to digital converter of claim 1, wherein the first stage includes an input capacitor and a feedback capacitor, and wherein the second stage reuses the same input capacitor and feedback capacitor.

7. The analog to digital converter of claim 6, wherein the second stage exhibits a positive feedback with a gain based on a ratio of the input capacitor and the feedback capacitor.

8. The analog to digital converter of claim 1, wherein the operational amplifier is a differential operational amplifier, and wherein the comparator is a differential comparator.

9. The analog to digital converter of claim 1, wherein the first stage includes a result counter, wherein an output of the comparator drives the result counter, wherein the second stage includes a result register, and wherein the output of the comparator drives the result register.

10. A method for performing analog to digital conversion, the method comprising:

performing a first analog to digital conversion using a delta-sigma based analog to digital converter, wherein the delta-sigma converter provides a first portion of a conversion result and a conversion residue;

performing a second analog to digital conversion using a Successive Approximation Register based analog to digital converter, wherein the Successive Approximation Resister based analog to digital converter operates on the conversion residue and provides a second portion of the conversion result; and

combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result;

wherein combining the first portion of the conversion result with the second portion of the conversion result includes performing a process selected from the group consisting of;

identifying the first portion of the conversion result as the most significant bits of the combined conversion result and identifying the second portion of the conversion result as the least significant bits of the combined conversion result; and

adding the first portion of the conversion result to the second portion of the conversion result, and wherein adding the first portion of the conversion result to the second portion of the conversion result includes shifting such that one or more most significant bits of the second portion of the conversion result are added to one or more least significant bits of the first portion of the conversion result.

11. A method for performing analog to digital conversion, the method comprising:

performing a first analog to digital conversion using a delta-sigma based analog to digital converter, wherein the delta-sigma converter provides a first portion of a conversion result and a conversion residue;

performing a second analog to digital conversion using a Successive Approximation Resister based analog to digital converter, wherein the Successive Approximation Register based analog to digital converter operates on the conversion residue and provides a second portion of the conversion result; and

combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result;

wherein performing the first analog to digital conversion using the delta-sigma based analog to digital converter includes performing a number of analog to digital conversion iterations, and wherein the number of analog to digital conversion iterations is greater than a number of bits in the combined conversion result.

12. The method of claim 11, wherein performing the second analog to digital conversion using the Successive Approximation Register based analog to digital converter includes performing a number of analog to digital conversion iterations, wherein the number of analog to digital conversion iterations is less than the number of bits in the combined conversion result.

13. The method of claim 12, wherein the number of Successive Approximation Register iterations is programmable.

14. The method of claim 11, wherein the number of delta-sigma iterations is programmable.

15. A method for performing analog to digital conversion, the method comprising:

performing a first analog to digital conversion using a delta-sigma based analog to digital converter, wherein the delta-sigma converter provides a first portion of a conversion result and a conversion residue;

performing a second analog to digital conversion using a Successive Approximation Register based analog to digital converter, wherein the Successive Approximation Register based analog to digital converter operates on the conversion residue and provides a second portion of the conversion result;

combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result; and

providing a differential analog to digital conversion circuit, wherein the differential analog to digital conversion circuit is configurable as a delta-sigma based analog to digital converter, and wherein the differential analog to digital conversion circuit is configurable as a Successive Approximation Register based analog to digital converter.

16. The method of claim 15, wherein the differential analog to digital conversion circuit includes a differential comparator and a differential operational amplifier, and wherein the differential comparator and the differential operational amplifier are used in both the delta-sigma based analog to digital convener and the Successive Approximation Register based analog to digital converter.

17. A analog to digital converter, the analog to digital converter comprising:

a differential operational amplifier;

a differential comparator, wherein an output of the differential operational amplifier is electrically coupled to an input of the differential comparator;

a first feedback capacitor and a second feedback capacitor; and

a group of switches, wherein the group of switches are selectable to configure the differential operational amplifier, the differential comparator, the first feedback capacitor, and the second feedback capacitor in a first operational mode;

wherein the first operational mode is a delta-sigma based analog to digital converter;

wherein the group of switches are further selectable to configure the differential operational amplifier, the differential comparator, the first feedback capacitor, and the second feedback capacitor in a second operational mode; and

wherein the second operational mode is operation as a Successive Approximation Register based analog to digital converter.

18. The analog to digital converter of claim 17, wherein the Successive Approximation Register based analog to digital converter produces an output selected from a group consisting of:

a single bit of resolution for each Successive Approximation Register cycle, and a single bit of resolution for each two Successive Approximation Register cycles.

19. The analog to digital converter of claim 17, wherein the Successive Approximation Register based analog to digital converter utilizes a comparator selected from a group consisting of:

a window comparator, and a single threshold comparator.

20. The analog to digital converter of claim 17, wherein the first stage includes a first input capacitor and a second input capacitor, and wherein the second stage reuses at least part of the first input capacitor and at least part of the second input capacitor.

21. The analog to digital converter of claim 20, wherein the second stage exhibits a positive feedback with a gain based on a ratio of the first input capacitor and the first feedback capacitor.