Non-volatile memory with background data latch caching during program operations

• US 7,505,320 B2
• Filed: 05/05/2006
• Issued: 03/17/2009
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Weinberg; Michael J
• Application Number:
  US11/382,006
• Publication Number:
  US 20060233022A1
• Time in Patent Office: 1,047 Days
• Field of Search: 365/185
• US Class Current: 365/185.12
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a write operation. In the exemplary embodiment, when the multiple phases of a write operation vary as to the number of states to track, a phase-dependent coding enables efficient utilization of the available data latches, thereby allowing a maximum of surplus latches for background cache operations.

Claims

1. A non-volatile memory device having addressable pages of memory cells, comprising:

a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

a control circuitry for controlling a current memory operation on the addressed page, said current memory operation having one or more phases during operation, each phase being associated with a predetermined set of operating states;

a phase-dependent coding provided for each phase so that for at least some of the phases, their set of operating states are coded with substantially a minimum of bits in order to free up a subset of free data latches; and

said control circuitry contemporaneously with the current memory operation, controlling one or more operations on the subset of free data latches with data related to one or more pending memory operations on the memory array.

2. The non-volatile memory device of claim 1, wherein the one or more operations on the subset of free data latches includes caching of the data related to one or more subsequent memory operations.

3. The non-volatile memory device claim 2, wherein the data related to one or more subsequent memory operations are supplied from external to the memory device.

4. The non-volatile memory device of claim 1, wherein the one or more operations on the subset of free data latches includes transferring of the data related to one or more subsequent memory operations into the subset of free data latches.

5. The non-volatile memory device of claim 2, wherein the one or more subsequent memory operations are program operations and the one or more operations on the subset of free data latches includes caching of the program data.

6. The non-volatile memory device of claim 2, wherein the data related to one or more subsequent memory operations are associated with another page distinct from the addressed page of memory cells.

7. The non-volatile memory device of claim 6, wherein the current memory operation is a program operation.

8. The non-volatile memory device of claim 2, wherein the data related to one or more subsequent memory operations are associated with the addressed page of memory cells.

9. The non-volatile memory device of claim 8, wherein the current memory operation is a program operation.

10. The non-volatile memory device of claim 2, wherein the data related to one or more subsequent memory operations are supplied by the memory device.

11. The non-volatile memory device of claim 2, wherein the one or more operations on the subset of free data latches includes transferring of the data related to one or more subsequent memory operations out of the subset of free data latches.

12. The non-volatile memory device of claim 2, wherein the one or more subsequent memory operations are read operations and the one or more operations on the subset of free data latches includes caching of the read data.

13. The non-volatile memory device of claim 2, wherein the data related to one or more subsequent memory operations are read data from another page distinct from the addressed page of memory cells.

14. The non-volatile memory device of claim 13, wherein the current memory operation is a program operation.

16. The non-volatile memory device of any one of claims 1-15, wherein the memory cells each stores one bit of data.

17. The non-volatile memory device of any one of claims 1-15, wherein the memory cells each stores two bits of data.

18. The non-volatile memory device of any one of claims 1-15, wherein the memory cells each stores more than two bits of data.

15. A non-volatile memory device having addressable pages of memory cells, comprising:

a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

means for controlling a current memory operation on the addressed page, said current memory operation having one or more phases during operation, each phase being associated with a predetermined set of operating states;

a phase-dependent coding provided for each phase so that for at least some of the phases, their set of operating states are coded with substantially a minimum of bits in order to free up a subset of free data latches; and

means for controlling one or more operations on the subset of free data latches with data related to one or more pending memory operations on the memory array contemporaneously with the current memory operation.