Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
First Claim
1. An integrated circuit comprising:
- a three-dimensional memory array having a first plane of memory cells disposed above a first dielectric layer disposed above a substrate, and having a second plane of memory cells disposed above a second dielectric layer disposed above the first memory plane, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings;
wherein each NAND string within a given memory plane includes a first switch device at a first end thereof for coupling the NAND string to an associated global bit line and further includes a second switch device at a second end thereof opposite the first end for coupling the NAND string to an associated bias node;
wherein a NAND string within the first memory plane and a NAND string within the second memory plane are vertically coupled to a global bit line disposed on a first interconnect layer, and are further vertically coupled to a bias node disposed on a second interconnect layer different than the first interconnect layer.
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Accused Products
Abstract
A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
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Citations
32 Claims
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1. An integrated circuit comprising:
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a three-dimensional memory array having a first plane of memory cells disposed above a first dielectric layer disposed above a substrate, and having a second plane of memory cells disposed above a second dielectric layer disposed above the first memory plane, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings; wherein each NAND string within a given memory plane includes a first switch device at a first end thereof for coupling the NAND string to an associated global bit line and further includes a second switch device at a second end thereof opposite the first end for coupling the NAND string to an associated bias node; wherein a NAND string within the first memory plane and a NAND string within the second memory plane are vertically coupled to a global bit line disposed on a first interconnect layer, and are further vertically coupled to a bias node disposed on a second interconnect layer different than the first interconnect layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A computer readable medium encoding an integrated circuit, said encoded integrated circuit comprising:
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a three-dimensional memory array having a first plane of memory cells disposed above a first dielectric layer disposed above a substrate, and having a second plane of memory cells disposed above a second dielectric layer disposed above the first memory plane, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings; wherein each NAND string within a given memory plane includes a first switch device at a first end thereof for coupling the NAND string to an associated global bit line and further includes a second switch device at a second end thereof opposite the first end for coupling the NAND string to an associated bias node; wherein a NAND string within the first memory plane and a NAND string within the second memory plane are vertically coupled to a global bit line disposed on a first interconnect layer, and are further vertically coupled to a bias node disposed on a second interconnect layer different than the first interconnect layer. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. An integrated circuit comprising:
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a three-dimensional memory array having at least two planes of memory cells formed above a dielectric layer that is formed above a substrate, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings; and a plurality of global array lines disposed on a layer of the integrated circuit, each of which is shared by at least one NAND string on each of at least two memory planes; a second plurality of array lines disposed on a second layer of the integrated circuit different than the first layer, each of said second plurality of array lines shared by a respective plurality of NAND strings on each of at least two memory planes; wherein each NAND string includes a first switch device at a first end thereof for coupling the NAND string to an associated global array line; and wherein the first switch device within a given NAND string is structurally substantially identical with the memory cell devices forming the given NAND string. - View Dependent Claims (29, 30, 31, 32)
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Specification