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Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

  • US 7,505,321 B2
  • Filed: 12/31/2002
  • Issued: 03/17/2009
  • Est. Priority Date: 12/31/2002
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a three-dimensional memory array having a first plane of memory cells disposed above a first dielectric layer disposed above a substrate, and having a second plane of memory cells disposed above a second dielectric layer disposed above the first memory plane, said memory cells comprising modifiable conductance switch devices arranged in a plurality of series-connected NAND strings;

    wherein each NAND string within a given memory plane includes a first switch device at a first end thereof for coupling the NAND string to an associated global bit line and further includes a second switch device at a second end thereof opposite the first end for coupling the NAND string to an associated bias node;

    wherein a NAND string within the first memory plane and a NAND string within the second memory plane are vertically coupled to a global bit line disposed on a first interconnect layer, and are further vertically coupled to a bias node disposed on a second interconnect layer different than the first interconnect layer.

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