DC offset correction using multiple configurable feedback loops

• US 7,505,744 B1
• Filed: 07/28/2005
• Issued: 03/17/2009
• Est. Priority Date: 07/28/2005
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Shan, Peijun
• Primary Examiner(s): NGUYEN, SIMON
• Application Number:
  US11/191,840
• Time in Patent Office: 1,328 Days
• Field of Search: 4552321-2511, 455/283, 455/296, 455/63.1, 455/317, 455323-325, 375317-319
• US Class Current: 455/130
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

The present invention provides a DC offset correction system for a wireless communication device that removes a DC offset from a baseband receive signal during “training time” when the baseband receive signal should ideally have no DC content. In general, the DC offset correction system includes multiple configurable feedback loops that operate to remove or cancel the DC offset from the baseband receive signal. One or more of the multiple configurable feedback loops is activated for a period of time during operation when it is known that the received signal should ideally contain no DC content. This training time varies depending on the particular communication standard being used by the wireless communication device. For example, the training time may be during reception of the preamble and header of an IEEE 802.11 packet.

Claims

1. A DC offset correction system for removing a DC offset of a wireless receiver comprising:

a plurality of nested configurable feedback loops each configurable to operate in either a tracking mode or a hold mode and adapted to;

a) track a DC offset of a baseband input signal provided by the wireless receiver to provide a DC offset correction signal when in the tracking mode; and

b) hold the DC offset correction signal constant when in the hold mode;

wherein at least one of the plurality of nested configurable feedback loops is configured in the tracking mode of operation during training time when the baseband input signal should have no DC content.

2. The system of claim 1 wherein the at least one of the plurality of nested configurable feedback loops is switched to the hold mode of operation at or before an end of the training time.

3. The system of claim 1 further comprising:

first differencing circuitry adapted to combine the baseband signal and a first DC offset correction signal to provide a corrected input signal; and

second differencing circuitry adapted to combine the corrected input signal and a second DC offset correction signal to provide an output signal;

wherein the plurality of nested configurable feedback loops comprise;

a configurable outer feedback loop adapted to low-pass filter the output signal to provide the first DC offset correction signal when the configurable outer feedback loop is in a tracking mode of operation, and hold the first DC offset correction signal constant when the configurable outer feedback loop is in a hold mode of operation; and

a configurable inner feedback loop adapted to low-pass filter the output signal to provide the second DC offset correction signal when the configurable inner feedback loop is in a tracking mode of operation, and hold the second DC offset correction signal constant when the configurable inner feedback loop is in a hold mode of operation.

4. The system of claim 3 wherein both the configurable outer feedback loop and the configurable inner feedback loop are configured in the tracking mode of operation during training time when the baseband signal should have no DC content.

5. The system of claim 3 wherein one of the configurable inner and outer feedback loops has a smaller scale and finer resolution than another of the configurable inner and outer feedback loops.

6. The system of claim 3 wherein the configurable outer feedback loop is a configurable analog feedback loop such that the first DC offset correction signal is an analog DC offset correction signal, and the configurable inner feedback loop is a configurable digital feedback loop such that the second DC offset correction signal is a digital DC offset correction signal.

7. The system of claim 6 wherein the DC offset correction system is configurable to operate in one of an analog mode where the configurable analog feedback loop is enabled and the configurable digital feedback loop is disabled, a digital mode where the configurable analog feedback loop is disabled and the configurable digital feedback loop is enabled, an analog and digital mode where both the configurable analog and digital feedback loops are enabled, or a no-correction mode where both the configurable analog and digital feedback loops are disabled.

8. The system of claim 6 wherein the DC offset correction system further comprises digitization circuitry adapted to digitize the corrected input signal to provide a digitized corrected input signal such that the second differencing circuitry combines the digitized corrected input signal and the digital DC offset correction signal to provide the output signal.

9. The system of claim 8 wherein the DC offset correction system further comprises:

first scaling circuitry having a first scaling factor (K) and adapted to scale the digitized corrected input signal to provide a scaled signal such that the second differencing circuitry combines the scaled signal and the digital DC offset correction signal to provide the output signal; and

second scaling circuitry having a second scaling factor (1/K) and adapted to scale the output signal to provide a scaled output signal, wherein the configurable digital feedback loop low-pass filters the scaled output signal to provide the second DC offset correction signal when the configurable digital feedback loop is in the tracking mode of operation.

10. The system of claim 8 wherein the configurable digital feedback loop comprises:

digital low-pass filtering circuitry adapted to low-pass filter the output signal to provide a filtered signal, the digital low-pass filtering circuitry controlled by a control signal such that the filtered signal is held constant when the configurable digital feedback loop is in the hold mode of operation and adjusted when the configurable digital feedback loop is in the tracking mode of operation; and

scaling circuitry adapted to scale the filtered signal to provide the digital DC offset correction signal.

11. The system of claim 10 wherein the scaling circuitry has a programmable scaling factor and the configurable digital feedback loop is enabled by setting the programmable scaling factor to a non-zero value and disabled by setting the programmable scaling factor to zero.

12. The system of claim 8 wherein the configurable analog feedback loop comprises:

digital low-pass filtering circuitry adapted to low-pass filter the output signal to provide a filtered signal, the digital low-pass filtering circuitry controlled by a control signal such that the filtered signal is held constant when the configurable analog feedback loop is in the hold mode of operation and adjusted when the configurable analog feedback loop is in the tracking mode of operation;

scaling circuitry adapted to scale the filtered signal to provide a scaled signal; and

digital-to-analog conversion circuitry adapted to process the scaled signal to provide the analog DC offset correction circuitry.

13. The system of claim 12 wherein the scaling circuitry has a programmable scaling factor and the configurable analog feedback loop is enabled by setting the programmable scaling factor to a non-zero value and disabled by setting the programmable scaling factor to zero.

14. The system of claim 1 wherein the DC offset correction system operates as a DC notch filter when the at least one of the plurality of nested configurable feedback loops is configured in the tracking mode of operation.

15. The system of claim 1 wherein the training time is a period of time during reception of a radio frequency signal when information communicated in the radio frequency signal according to a communication standard is such that the baseband signal should ideally contain no DC content.

16. The system of claim 1 wherein the wireless receiver operates according to the IEEE 802.11 communication standard and the training time corresponds to at least one of a preamble and header of packet communicated in a radio frequency signal received by the wireless receiver.

17. A method for correcting a DC offset of a wireless receiver comprising:

providing a plurality of nested configurable feedback loops each configurable in either a tracking mode or a hold mode and adapted to track a DC offset of a baseband input signal provided by the wireless receiver to provide a DC offset correction when in the tracking mode and further adapted to hold the DC offset correction constant when in the hold mode; and

configuring at least one of the plurality of nested configurable feedback loops in the tracking mode of operation during training time when the baseband input signal should have no DC content.

18. The method of claim 17 further comprising switching the at least one of the plurality of nested configurable feedback loops to the hold mode of operation at or before an end of the training time.

19. A method for removing a DC offset from a baseband signal provided by a wireless receiver comprising:

combining the baseband signal and a first DC offset correction signal to provide a corrected input signal;

combining the corrected input signal and a second DC offset correction signal to provide an output signal;

processing the output signal to provide the first DC offset correction signal during a training time when the baseband signal should ideally contain no DC content;

holding the first DC offset correction signal constant to provide the first DC offset correction signal after the training time;

processing the output signal to provide the second DC offset correction signal during the training time when the baseband signal should ideally contain no DC content; and

holding the second DC offset correction signal constant to provide the first DC offset correction signal after the training time.

20. The method of claim 19 wherein processing the output signal to provide the first DC offset correction signal has a larger scale and finer resolution than processing the output signal to provide the second DC offset correction signal.