Optimized placement policy for solid state storage devices
First Claim
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1. An apparatus for data storage comprising:
- a plurality of flash buses;
a plurality of DMA Engines coupled to at least two of the plurality of flash buses;
a plurality of flash devices coupled to at least two of the plurality of DMA Engines;
wherein data access performance is improved by bus interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two flash buses;
wherein data access performance is improved by flash array bank interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two DMA Engines;
wherein data access performance is improved by group interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two flash devices;
wherein each of the plurality of flash devices further comprises a plurality of sections;
wherein each section in the apparatus is operable to be accessed using a physical block address comprising a least significant portion, a second least significant portion, a third least significant portion, and a fourth least significant portion;
wherein the least significant portion comprises an order according to the plurality of flash buses, the second least significant portion comprises an order according to a plurality of DMA Engines each coupled to a same flash bus, the third least significant portion comprises an order according to a plurality of flash devices each coupled to a same DMA Engine, and the fourth least significant portion comprises an order according to the plurality of sections in a same flash device; and
wherein a logical block address for host data access is mapped to a physical block address according to a placement algorithm whereby host data access performance is improved.
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Abstract
A data storage system is provided comprising several flash arrays in a board and stacking these boards to attain a high-capacity solid state hard drive. A remap table is used to map all logical addresses from a host system to the actual physical addresses where data are stored. The assignments of these physical locations are done in such a way that the load of the system is evenly distributed to its available resources. This would ensure that the storage system will run at its utmost efficiency utilizing its resources properly. To achieve this, the system would make sure that the physical location of data be evenly distributed according to the current load of the system.
59 Citations
7 Claims
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1. An apparatus for data storage comprising:
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a plurality of flash buses; a plurality of DMA Engines coupled to at least two of the plurality of flash buses; a plurality of flash devices coupled to at least two of the plurality of DMA Engines; wherein data access performance is improved by bus interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two flash buses; wherein data access performance is improved by flash array bank interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two DMA Engines; wherein data access performance is improved by group interleaving wherein one or more data is transferred to or from the plurality of flash devices using at least two flash devices; wherein each of the plurality of flash devices further comprises a plurality of sections; wherein each section in the apparatus is operable to be accessed using a physical block address comprising a least significant portion, a second least significant portion, a third least significant portion, and a fourth least significant portion; wherein the least significant portion comprises an order according to the plurality of flash buses, the second least significant portion comprises an order according to a plurality of DMA Engines each coupled to a same flash bus, the third least significant portion comprises an order according to a plurality of flash devices each coupled to a same DMA Engine, and the fourth least significant portion comprises an order according to the plurality of sections in a same flash device; and wherein a logical block address for host data access is mapped to a physical block address according to a placement algorithm whereby host data access performance is improved. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification