Decompressor/PRPG for applying pseudo-random and deterministic test patterns

• US 7,506,232 B2
• Filed: 08/11/2006
• Issued: 03/17/2009
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US11/502,655
• Publication Number:
  US 20070011530A1
• Time in Patent Office: 949 Days
• Field of Search: 714/741, 714/738, 714/728
• US Class Current: 714/728
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Claims

1. A method for testing a circuit-under-test, comprising:

simulating a pseudo-random phase of operation of the circuit-under-test, wherein the simulation comprises simulating faults in the circuit-under-test while pseudo-random test patterns are applied to the circuit-under-test;

identifying faults that are undetected by the pseudo-random phase of operation using results from the simulation; and

producing one or more compressed deterministic test patterns that target at least some of the faults that are undetected during the pseudo-random phase of operation, the compressed deterministic test patterns being applicable to the circuit-under-test during a deterministic phase of operation.

2. The method of claim 1, further comprising,

providing at least one of the compressed deterministic test patterns to the circuit-under-test;

and

simultaneously decompressing the at least one of the compressed deterministic test patterns as the at least one of the compressed deterministic test patterns is being provided.

3. The method of claim 2, wherein an external tester provides the at least one of the compressed deterministic test patterns.

4. The method of claim 2, wherein a decompressor/PRPG simultaneously decompresses the at least one of the compressed deterministic test patterns, and wherein the decompressor/PRPG is operable to receive from an external tester the compressed deterministic test patterns for use in the deterministic phase of operation and an initial seed value for use in the pseudo-random phase of operation.

5. The method of claim 1, wherein at least one of the compressed deterministic test patterns is generated from a test cube.

6. An automatic test pattern generation (ATPG) tool configured to produce compressed deterministic test patterns according to the method of claim 1.

7. An automatic test pattern generation (ATPG) tool configured to perform a method, the method comprising:

simulating a pseudo-random phase of operation of the circuit-under-test, wherein the simulation comprises simulating faults in the circuit-under-test while pseudo-random test patterns are applied to the circuit-under-test;

identifying faults that are undetected by the pseudo-random phase of operation using results from the simulation; and

producing one or more compressed deterministic test patterns that target at least some of the faults that are undetected during the pseudo-random phase of operation, the compressed deterministic test patterns being applicable to the circuit-under-test during a deterministic phase of operation.

8. The ATPG tool of claim 7, wherein the compressed deterministic test patterns are applicable to a decompressor that simultaneously decompresses the at least one of the compressed deterministic test patterns as the at least one of the compressed deterministic test patterns is being provided to the decompressor.

9. The ATPG tool of claim 7, wherein the act of producing one or more compressed deterministic test patterns comprises determining a partially specified test cube that targets one or more of the identified faults.

10. The ATPG tool of claim 7, wherein the act of producing one or more compressed deterministic test patterns comprises solving linear equations to determine the compressed deterministic test patterns.

11. The ATPG tool of claim 7, wherein at least one of the compressed deterministic test patterns is generated from a test cube.

12. One or more compressed deterministic test patterns produced by the method of claim 7.