Decompressor/PRPG for applying pseudo-random and deterministic test patterns
First Claim
1. A method for testing a circuit-under-test, comprising:
- simulating a pseudo-random phase of operation of the circuit-under-test, wherein the simulation comprises simulating faults in the circuit-under-test while pseudo-random test patterns are applied to the circuit-under-test;
identifying faults that are undetected by the pseudo-random phase of operation using results from the simulation; and
producing one or more compressed deterministic test patterns that target at least some of the faults that are undetected during the pseudo-random phase of operation, the compressed deterministic test patterns being applicable to the circuit-under-test during a deterministic phase of operation.
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Abstract
A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
171 Citations
12 Claims
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1. A method for testing a circuit-under-test, comprising:
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simulating a pseudo-random phase of operation of the circuit-under-test, wherein the simulation comprises simulating faults in the circuit-under-test while pseudo-random test patterns are applied to the circuit-under-test; identifying faults that are undetected by the pseudo-random phase of operation using results from the simulation; and producing one or more compressed deterministic test patterns that target at least some of the faults that are undetected during the pseudo-random phase of operation, the compressed deterministic test patterns being applicable to the circuit-under-test during a deterministic phase of operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An automatic test pattern generation (ATPG) tool configured to perform a method, the method comprising:
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simulating a pseudo-random phase of operation of the circuit-under-test, wherein the simulation comprises simulating faults in the circuit-under-test while pseudo-random test patterns are applied to the circuit-under-test; identifying faults that are undetected by the pseudo-random phase of operation using results from the simulation; and producing one or more compressed deterministic test patterns that target at least some of the faults that are undetected during the pseudo-random phase of operation, the compressed deterministic test patterns being applicable to the circuit-under-test during a deterministic phase of operation. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification