Method and mechanism for implementing DFM aware cells for an electronic design
First Claim
1. A method of allowing relaxed design rules when implementing an integrated circuit design, comprising:
- defining a design for manufacturing (DFM) rule, the DFM rule corresponding to an alternate design rule from minimum design rule check (DRC) rules;
defining a set of one or more of the DFM rules as a constraint group;
associating the constraint group with an intelligent design parameterized cell master;
applying the constraint group on an instance of the intelligent design parameterized cell master to an intelligent design cell to override a default DRC rule for the integrated circuit design; and
performing layout of the integrated circuit design.
1 Assignment
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Accused Products
Abstract
An improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and improve the layout productivity is disclosed. In some disclosed approaches, automated interactive aids and batch tools are provided which can assist in optimizing the final layouts for yield at the initial placement and/or routing stages for optimizing yield. Provided in some disclosed approaches are automated capability to layout designers at the mos devices level to configure mos devices as per different DFY recommendations from the foundry without negative effects on the overall chip area (or cell size). The design rules may be relaxed selectively on an instance basis and wherever possible or desirable.
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Citations
20 Claims
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1. A method of allowing relaxed design rules when implementing an integrated circuit design, comprising:
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defining a design for manufacturing (DFM) rule, the DFM rule corresponding to an alternate design rule from minimum design rule check (DRC) rules; defining a set of one or more of the DFM rules as a constraint group; associating the constraint group with an intelligent design parameterized cell master; applying the constraint group on an instance of the intelligent design parameterized cell master to an intelligent design cell to override a default DRC rule for the integrated circuit design; and performing layout of the integrated circuit design. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer program product comprising a tangible computer usable medium having executable code to execute a process for allowing relaxed design rules when implementing an integrated circuit design, the process comprising:
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defining a design for manufacturing (DFM) rule, the DFM rule corresponding to an alternate design rule from minimum design rule check (DRC) rules; defining a set of one or more of the DFM rules as a constraint group; associating the constraint group with an intelligent design parameterized cell master; applying the constraint group on an instance of the intelligent design parameterized cell master to an intelligent design cell to override a default DRC rule for the integrated circuit design; and performing layout of the integrated circuit design. - View Dependent Claims (17)
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18. A system for allowing relaxed design rules when implementing an integrated circuit design, comprising:
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means for defining a design for manufacturing (DFM) rule, the DFM rule corresponding to an alternate design rule from minimum design rule check (DRC) rules; means for defining a set of one or more of the DFM rules as a constraint group; means for associating the constraint group with an intelligent design parameterized cell master; means for applying the constraint group on an instance of the intelligent design parameterized cell master to an intelligent design cell to override a default DRC rule for the integrated circuit design; and means for performing layout of the integrated circuit design. - View Dependent Claims (19, 20)
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Specification