Method of forming a MEMS inductor with very low resistance

• US 7,507,589 B1
• Filed: 06/21/2007
• Issued: 03/24/2009
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Johnson, Peter, Hopper, Peter J., Hwang, Kyuwoon, Drury, Robert
• Primary Examiner(s): Lindsay, Jr.; Walter L
• Assistant Examiner(s): Lee; Cheung
• Application Number:
  US11/820,921
• Time in Patent Office: 642 Days
• Field of Search: 438/171, 438/190, 438/329
• US Class Current: 438/3
• CPC Class Codes: H01F 10/14 containing iron or nickel H01F10/126 , H01F10/13, H01F10/16 take precedence
• CPC Class Codes: H01F 10/265 Magnetic multilayers non exchange-coupled H01F10/32 takes precedence
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01F 41/309 electroless or electrodeposition processes from plating solution

Abstract

A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.

Claims

1. A method of forming a semiconductor structure comprising:

forming a first conductive plate that touches a dielectric layer, the first conductive plate having a first side region and a second side region that lies opposite to and spaced apart from the first side region; and

forming a conductive structure, the conductive structure having;

a second conductive plate that lies over and is spaced apart from the first conductive plate, the second conductive plate having a first side region and a second side region that lies opposite to and spaced apart from the first side region of the second conductive plate;

a first side wall that touches the second side region of the first conductive plate and the second side region of the second conductive plate; and

a second side wall that touches the first side region of the second conductive plate, the second side wall lying laterally adjacent to and spaced apart from the first side region of the first conductive plate.

2. The method of claim 1 wherein the first side region of the first conductive plate touches a first via.

3. The method of claim 2 wherein the second side wall touches a second via that lies laterally adjacent to the first via.

4. The method of claim 2 wherein forming a conductive structure includes forming an opening that exposes the second side region of the first conductive plate, and an opening that exposes a second via that lies adjacent to the first via.

5. The method of claim 2 and further comprising:

forming an isolation layer on the dielectric layer and the first conductive plate to cover the first conductive plate;

forming an opening in the isolation layer over the first conductive plate, the opening having a bottom surface spaced apart from a top surface of the first conductive plate.

6. The method of claim 5 wherein the opening lies only over the first conductive plate.

7. The method of claim 5 wherein forming a conductive structure includes forming an opening in the isolation layer to expose the second side region of the first conductive plate, and an opening in the isolation layer and the dielectric layer to expose a second via that lies adjacent to the first via.

8. The method of claim 1 wherein the first side region of the first conductive plate touches a plurality of spaced-apart laterally-adjacent first vias.

9. The method of claim 8 wherein the second side wall touches a plurality of laterally-adjacent second vias that lie laterally adjacent to the plurality of first vias.

10. The method of claim 1 wherein an interior region is defined to lie only between the first conductive plate and the second conductive plate, between the first side wall and the second side wall, and be spaced apart from the first conductive plate, the second conductive plate, the first side wall, and the second side wall, the interior region being electrically isolated from all non-interior regions.

11. The method of claim 1 wherein forming a first conductive plate includes:

forming a dielectric opening in the dielectric layer, the dielectric opening having a first side and a second side that lies opposite to the first side of the dielectric opening; and

forming the first conductive plate in the dielectric opening.

12. The method of claim 11 wherein the dielectric opening exposes a plurality of laterally-adjacent vias that lie along the first side of the dielectric opening.

13. The method of claim 12 wherein the first conductive plate includes copper.

14. The method of claim 1 wherein forming a conductive structure includes forming an opening that exposes the second side region of the first conductive plate.