Closed-grid bus architecture for wafer interconnect structure
First Claim
1. An apparatus for providing electrically conductive paths for test signals, said apparatus comprising:
- a substrate;
a plurality of electrically conductive terminals disposed on said substrate;
a plurality of electrically conductive traces disposed on said substrate, ones of said traces being electrically connected to ones of said terminals;
a plurality of electrically conductive probes; and
a plurality of thin film resistors, ones of said thin film resistors electrically connecting one of said traces with ones of said plurality of said probes,wherein said one of said traces is part of a bus structure that electrically connects one of said terminals to said ones of said probes, said bus structure providing a plurality of different conductive paths between said one of said terminals and at least one of said probes.
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Abstract
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.
64 Citations
9 Claims
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1. An apparatus for providing electrically conductive paths for test signals, said apparatus comprising:
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a substrate; a plurality of electrically conductive terminals disposed on said substrate; a plurality of electrically conductive traces disposed on said substrate, ones of said traces being electrically connected to ones of said terminals; a plurality of electrically conductive probes; and a plurality of thin film resistors, ones of said thin film resistors electrically connecting one of said traces with ones of said plurality of said probes, wherein said one of said traces is part of a bus structure that electrically connects one of said terminals to said ones of said probes, said bus structure providing a plurality of different conductive paths between said one of said terminals and at least one of said probes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification