Driving circuit that eliminates effects of ambient temperature variations and increases driving capacity

• US 7,508,242 B2
• Filed: 02/01/2007
• Issued: 03/24/2009
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Tokuno, Yoshio
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US11/700,835
• Publication Number:
  US 20070229124A1
• Time in Patent Office: 782 Days
• Field of Search: 327/108, 327/112, 326/83
• US Class Current: 327/108
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

In addition to two-stage CMOS inverters inverting and amplifying the input signal, a rising edge detector detects the rising edge of the input signal, and outputs a rising edge detection signal having a pulse width corresponding to ambient temperature, a PMOS drives the output node to the power supply potential according to the rising edge detection signal, a falling edge detector detects the falling edge of the input signal and outputs a falling edge detection signal having a pulse width corresponding to ambient temperature, and an NMOS drives the output node to ground potential according to the falling edge detection signal. When ambient temperature rises, and delay time of the inverters are thereby increased, pulse widths of the rising and falling edge detection signals are increased. The additional driving restrains delay time variation in a driving circuit due to ambient temperature change.

Claims

1. A driving circuit comprising:

a driving section for buffering an input signal at an input node, and outputting an amplified signal to an output node;

a rising edge detector for detecting a rising edge of the input signal and outputting a first detection signal having a pulse width corresponding to ambient temperature; and

a first transistor connected between the output node and a power supply potential node, and controlled to be conductive according to the first detection signal,

wherein said driving section comprises a first inverter receiving the input signal at the input node, and a second inverter receiving an output of the first inverter and having an output connected to the out node, and

said rising edge detector comprises a third inverter receiving the input signal at the input node, and a NAND gate having one input receiving the input signal at the input node, having another input receiving an output of the third inverter and having an output connected to a gate of the first transistor.

2. The driving circuit according to claim 1, further comprising:

a falling edge detector for detecting a falling edge of the input signal and outputting a second detection signal having a pulse width corresponding to the ambient temperature; and

a second transistor connected between the output node and a ground potential node, and controlled to be conductive according to the second detection signal,

wherein said falling edge detector comprises a fourth inverter receiving the input signal at the input node, and a NOR gate having one input receiving the input signal at the input node, having another input receiving an output of the fourth inverter and having an output connected to a gate of the second transistor.

3. A driving circuit comprising:

a driving section buffering an input signal at an input node, and outputting an amplified signal to an output node;

a first level detector for detecting a rising edge and a falling edge of the input signal and outputting a first detection signal which changes to one logic state a certain time interval after the detection of the rising edge of the input signal and changes to another logic state upon detection of the falling edge of the input signal; and

a first transistor connected between the output node and a power supply potential node, and controlled to be conductive according to the first detection signal,

wherein said driving section comprises a first inverter receiving the input signal at the input node, and a second inverter receiving an output of the first inverter and having an output connected to the output node, and

said first level detector comprises a first delay element receiving the input signal at the input node, and a NAND gate having one input receiving the input signal at the input node, having another input receiving an output of the first delay element and having an output connected to a gate of the first transistor.

4. The driving circuit according to claim 3, further comprising:

a second level detector for detecting the falling edge and the rising edge of the input signal and outputting a second detection signal which changes to one logic state a certain time interval after the detection of the falling edge of the input signal and changes to another logic state upon detection of the rising edge of the input signal; and

a second transistor connected between the output node and a ground potential node, and controlled to be conductive according to the second detection signal,

wherein said second level detector comprises a second delay element receiving the input signal at the input node, and a NOR gate having one input receiving the input signal at the input node, having another input receiving an output of the second delay element and having an output connected to a gate of the second transistor.

5. A driving circuit comprising:

a first inverter receiving an input signal at an input node, and including a first P-channel MOS transistor and a first N-channel MOS transistor both connected between a power supply potential node and a ground potential node;

a second inverter receiving an output of the first inverter, having an output connected to an output node, and including a second P-channel MOS transistor and a second N-channel MOS transistor both connected between the power supply potential node and the ground potential node;

a third P-channel MOS transistor connected between the output node and the power supply potential node;

a third N-channel MOS transistor connected between the output node and the ground potential node;

a rising edge detector for detecting a rising edge of the input signal, and outputting a first detection signal which falls upon detection of the rising edge of the input signal and rises a first certain time interval after the rising edge of the input signal, said first certain time interval corresponding to ambient temperature; and

a falling edge detector for detecting a falling edge of the input signal, and outputting a second detection signal which rises upon detection of the falling edge of the input signal and falls a second certain time interval after the falling edge of the input signal, said second certain time interval corresponding to ambient temperature,

wherein said third P-channel MOS transistor is conductive when the first detection signal is low,

said third N-channel MOS transistor is conductive when the second detection signal is high,

said rising edge detector comprises a third inverter receiving the input signal at the input node, and a NAND gate having one input receiving the input signal at the input node, having another input receiving an output of the third inverter and having an output connected to a gate of the third P-channel MOS transistor, and

said falling edge detector comprises a fourth inverter receiving the input signal at the input node, and a NOR gate having one input receiving the input signal at the input node, having another input receiving an output of the fourth inverter and having an output connected to a gate of the third N-channel MOS transistor.

6. A driving circuit comprising:

a first inverter receiving an input signal at an input node, and including a first P-channel MOS transistor and a first N-channel MOS transistor connected between a power supply potential node and a ground potential node;

a second inverter receiving an output of the first inverter, having an output connected to an output node, and including a second P-channel MOS transistor and a second N-channel MOS transistor both connected between the power supply potential node and the ground potential node;

a third P-channel MOS transistor connected between the output node and the power supply potential node;

a third N-channel MOS transistor connected between the output node and the ground potential node;

a first level detector for detecting a rising edge and a tailing edge of the input signal, and outputting a first detection signal which rises a first certain time interval after the detection of the rising edge of the input signal and falls upon detection of the falling edge of the input signal; and

a second level detector for detecting a falling edge and a rising edge of the input signal, and outputting a second detection signal which falls a second certain time interval after the detection of the rising edge of the input signal and rises upon detection of the falling edge of the input signal,

wherein said third P-channel MOS transistor is conductive when the first detection signal is low,

said third N-channel MOS transistor is conductive when the second detection signal is high,

said first level detector comprises a first delay element receiving the input signal at the input node, and a NAND gate having one input receiving the input signal at the input node, having another input receiving an output of the first delay element and having an output connected to a gate of the third P-channel MOS transistor, and

said second level detector comprises a second delay element receiving the input signal at the input node, and a NOR gate having one input receiving the input signal at the input node, having another input receiving an output of the second delay element and having an output connected to a gate of the third N-channel MOS transistor.