Tuning of a phase-locked loop, and an electronic device

• US 7,508,244 B2
• Filed: 06/30/2006
• Issued: 03/24/2009
• Est. Priority Date: 05/31/2006
• Status: Expired due to Fees

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Nokia Corporation
• Inventors: Hallivuori, Juha
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US11/477,765
• Publication Number:
  US 20070279110A1
• Time in Patent Office: 998 Days
• Field of Search: None
• US Class Current: 327/156
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

There is provided an electronic device comprising: a control block for providing a control signal; a voltage-controlled oscillator; a divider block; a detector block for receiving a frequency-divided output signal from the divider block, for receiving a reference frequency signal and for providing a feedback control signal to the voltage-controlled oscillator. The voltage-controlled oscillator is further configured to include a frequency offset to the voltage-controlled oscillator output signal; and the control block is further configured to control the frequency offset included in the voltage-controlled oscillator output signal on the basis of fractional division ratio information and actual division state information received from the phase-locked loop.

Claims

1. An apparatus comprising:

a control block configured to provide a control signal;

a voltage-controlled oscillator configured to receive the control signal and to output an output signal;

a divider block configured to receive the output signal from the voltage-controlled oscillator and configured to divide a frequency of the output signal by a predetermined number;

a detector block configured to

receive a frequency-divided output signal from the divider block,

receive a reference frequency signal, and

provide a feedback control signal to the voltage-controlled oscillator in a phase-locked loop,

wherein the voltage-controlled oscillator is further configured to include a frequency offset in the voltage-controlled oscillator output signal,

wherein the control block is further configured to control the frequency offset included in the voltage-controlled oscillator output signal based on fractional division ratio information and actual division state information received from the phase-locked loop, and

the phase-locked loop further comprising one or more resettable delay components configured to remove incorrect frequencies from the voltage-controlled oscillator output signal.

2. The apparatus of claim 1, wherein the control block is further configured to remove a detected incorrect frequency from the voltage-controlled oscillator output signal by resetting the delay components with the incorrect frequency and by connecting a correct frequency with a correct phase by tuning an individual delay.

3. An apparatus comprising:

a control block configured to provide a control signal;

a voltage-controlled oscillator configured to receive the control signal and to output an output signal;

a divider block configured to receive the output signal from the voltage-controlled oscillator and configured to divide a frequency of the output signal by a predetermined number;

a detector block configured to

receive a frequency-divided output signal from the divider block,

receive a reference frequency signal, and

provide a feedback control signal to the voltage-controlled oscillator in a phase-locked loop,

wherein the voltage-controlled oscillator is further configured to include a frequency offset in the voltage-controlled oscillator output signal,

wherein the control block is further configured to control the frequency offset included in the voltage-controlled oscillator output signal based on fractional division ratio information and actual division state information received from the phase-locked loop, and

wherein the divider block is configured to provide an extra digital control to the output signal, the extra digital control being a simple bit.

4. An apparatus comprising:

a control block configured to provide a control signal;

a voltage-controlled oscillator configured to receive the control signal and to output an output signal;

a divider block configured to receive the output signal from the voltage-controlled oscillator and configured to divide a frequency of the output signal by a predetermined number;

a detector block configured to

receive a frequency-divided output signal from the divider block,

receive a reference frequency signal, and

provide a feedback control signal to the voltage-controlled oscillator in a phase-locked loop,

wherein the voltage-controlled oscillator is further configured to include a frequency offset in the voltage-controlled oscillator output signal,

wherein the control block is further configured to control the frequency offset included in the voltage-controlled oscillator output signal based on fractional division ratio information and actual division state information received from the phase-locked loop, and

wherein the overall fractional division ratio provided by the phase-locked loop is based on an amount of calculated signal edges in the divider block, the received frequency control signal and a state change time.

5. A method comprising:

providing, by a control block, a control signal;

receiving, by a voltage-controlled oscillator, the control signal and outputting an output signal;

receiving, by a divider block, the output signal from the voltage-controlled oscillator and dividing a frequency of the output signal by a predetermined number;

receiving, by a detector block, a frequency-divided output signal from the divider block, receiving a reference frequency signal and providing a feedback control signal to the voltage-controlled oscillator in a phase-locked loop;

including a frequency offset to the voltage-controlled oscillator output signal by the voltage-controlled oscillator;

controlling, by the control block, the frequency offset included in the voltage-controlled oscillator output signal based on fractional division ratio information and actual division state information received from the phase-locked loop; and

removing incorrect frequencies from the voltage-controlled oscillator output signal by one or more resettable delay components of the phase-locked loop.

6. The method of claim 5, further comprising removing a detected incorrect frequency from the voltage-controlled oscillator output signal by resetting the delay components with the incorrect frequency and by connecting a correct frequency with a correct phase by tuning an individual delay.

7. A method comprising:

providing, by a control block, a control signal;

receiving, by a voltage-controlled oscillator, the control signal and outputting an output signal;

receiving, by a divider block, the output signal from the voltage-controlled oscillator and dividing a frequency of the output signal by a predetermined number;

receiving, by a detector block, a frequency-divided output signal from the divider block, receiving a reference frequency signal and providing a feedback control signal to the voltage-controlled oscillator in a phase-locked loop;

including a frequency offset to the voltage-controlled oscillator output signal by the voltage-controlled oscillator; and

controlling, by the control block, the frequency offset included in the voltage-controlled oscillator output signal based on fractional division ratio information and actual division state information received from the phase-locked loop,

wherein the overall fractional division ratio provided by the phase-locked loop is based on an amount of calculated signal edges in the divider block, the received frequency control signal and a state change time.