Self-repairing technique in nano-scale SRAM to reduce parametric failures

• US 7,508,697 B1
• Filed: 05/09/2007
• Issued: 03/24/2009
• Est. Priority Date: 05/09/2007
• Status: Expired due to Fees

• Current Assignee: Purdue Research Foundation (Purdue University)
• Original Assignee: Purdue Research Foundation (Purdue University)
• Inventors: Mukhopadhyay, Saibal, Mahmoodi, Hamid, Kim, Keejong, Roy, Kaushik
• Primary Examiner(s): Ho; Hoai V
• Application Number:
  US11/746,448
• Time in Patent Office: 685 Days
• Field of Search: 365/154, 365/189.7, 365/189.09
• US Class Current: 365/154
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die V_t process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die V_t process corner, thereby reducing possible access and write failures.

Claims

1. A self-repairing SRAM, comprising:

an array of SRAM cells;

an on-chip leakage monitor selectively coupled to said SRAM array for measuring the standby leakage current of the array;

a comparator responsive to an output signal from said leakage monitor for comparing said output signal to reference values corresponding to low and high inter-die V_t process corners; and

a body bias generator having an input coupled to said comparator and an output coupled to a body bias input of said array,

wherein said comparator supplies a control signal to said input of said body bias generator to cause said body bias generator to apply reverse body bias (RBB) in an array from a low inter-die V_t process corner and to apply forward body bias (FBB) in an array from a high inter-die V_t process corner.

2. A self-repairing SRAM, comprising:

an array of SRAM cells on a die;

a long inverter chain on the die with said array, said inverter chain having an input and an output;

a counter having first and second inputs connected respectively to said input and said output of said inverter chain, said counter measuring the delay in signal propagation through said inverter chain;

a comparator coupled to said counter for comparing the delay to reference values corresponding to low and high inter-die V_t process corners; and

a body bias generator having an input coupled to said comparator and an output coupled to a body bias input of said array,

wherein said comparator supplies a control signal to said input of said body bias generator to cause said body bias generator to apply reverse body bias (RBB) in an array from a low inter-die V_t process corner and to apply forward body bias (FBB) in an array from a high inter-die V_t process corner.

3. A method of reducing parametric failures in SRAM, comprising:

measuring the standby leakage current of a SRAM array with an on-chip leakage monitor;

comparing the leakage current of the array to reference values corresponding to low and high inter-die V_t process corners;

applying reverse body bias (RBB) to the array if the comparison indicates a low inter-die V_t process corner; and

applying forward body bias (FBB) to the array if the comparison indicates a high inter-die V_t process corner.

4. A method of reducing parametric failures in SRAM, comprising:

providing a long inverter chain on a die with an array of SRAM cells;

measuring the delay in signal propagation through the inverter chain;

comparing the delay to reference values corresponding to low and high inter-die V_t process corners;

applying reverse body bias (RBB) to the SRAM array if the comparison indicates a low inter-die V_t process corner; and

applying forward body bias (FBB) to the SRAM array if the comparison indicates a high inter-die V_t process corner.