Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block

• US 7,508,714 B2
• Filed: 05/21/2007
• Issued: 03/24/2009
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Chen, En-Hsing, Scheuerlein, Roy E., Fasoli, Luca G., Nallamothu, Sucheta, Mahajani, Maitreyee, Walker, Andrew J.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/751,567
• Publication Number:
  US 20070217263A1
• Time in Patent Office: 673 Days
• Field of Search: 365/51, 365/63, 365/185.05, 365/185.06, 365/185.18, 365/230.03
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Abstract

An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

Claims

1. An integrated circuit comprising:

a memory array having at least two planes of memory cells formed above a substrate, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof;

wherein each respective NAND string within a given memory block of a given memory plane is coupled to a respective global bit line that is not shared by other NAND strings within the given memory block of the given memory plane, and wherein some adjacent NAND strings within a memory block are coupled at opposite ends thereof to their respective global bit lines;

wherein half of said NAND strings within the given memory block are each coupled at one end thereof to its respective global bit line, and the other half of said NAND strings within the given memory block are each coupled at the other end thereof to its respective global bit line;

wherein each NAND string of a first group of M adjacent NAND strings within the given memory block is coupled at one end thereof to its respective global bit line, and each NAND string of an adjacent second group of M adjacent NAND strings within the given memory block is coupled at the other end thereof to its respective global bit line; and

wherein a respective NAND string within the first group of M adjacent NAND strings is adjacent to a respective NAND string within the second group of M adjacent NAND strings, and are coupled at opposite ends thereof to their respective global bit lines.

2. The integrated circuit of claim 1 wherein:

NAND strings of a group of M adjacent NAND strings within the given memory block share a single zia coupled to an associated bias node.

3. The integrated circuit of claim 2 wherein M =2.

4. The integrated circuit of claim 2 further comprising NAND strings having an identical pitch as respective global bit lines associated therewith.

5. The integrated circuit of claim 2 wherein the memory cell devices and series selection devices forming each NAND string are structurally substantially identical.

6. The integrated circuit of claim 2 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.

7. The integrated circuit of claim 2 wherein the substrate comprises a polycrystalline substrate or an insulating substrate.

8. The integrated circuit of claim 2 wherein the thin film modifiable conductance switch devices comprise silicon nanoparticles, a polarizable material, or a ferroelectric material.

9. The integrated circuit of claim 2 wherein said switch devices include a charge storage dielectric.

10. The integrated circuit of claim 9 wherein said charge storage dielectric comprises an oxide-nitride-oxide dielectric stack.

15. The integrated circuit of claim 1 wherein adjacent NAND strings are respectively coupled to a respective global bit line by way of a respective zia structure having a pitch matching that of the NAND strings.

16. The integrated circuit of claim 1 embodied in computer readable descriptive form suitable for design, test, or fabrication of the integrated circuit.

11. An integrated circuit comprising:

a memory array having at least two planes of memory cells formed above a substrate, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said NAND strings including a series select device at each end thereof; and

a plurality of bias nodes;

wherein each respective NAND string within a given memory block of a given memory plane is coupled to a respective global bit line that is not shared by other NAND strings within the given memory block of the given memory plane, and wherein some adjacent NAND strings within a memory block are coupled at opposite ends thereof to their respective global bit lines; and

wherein NAND strings within a respective memory block on two or more memory planes are coupled to an associated bias node.

12. The integrated circuit of claim 11 wherein said memory array further comprises:

a first plurality of zias, each of said first plurality of zias respectively coupling a first end of a respective NAND string on each of two or more memory planes to a respective global bit line; and

a second plurality of zias, each of said second plurality of zias respectively coupling a second end of a respective NAND string on each of two or more memory planes to an associated bias node.

13. The integrated circuit of claim 12 wherein said memory array further comprises:

a plurality of global bit lines, each coupled to respective NAND strings on each of two or more memory planes.

14. The integrated circuit of claim 12 further comprising:

a respective plurality of global bit lines disposed on each of two global bit line layers, said global bit lines having approximately twice the pitch of said NAND strings.

17. The integrated circuit of claim 11 wherein adjacent NAND strings are respectively coupled to a respective global bit line by way of a respective zia structure having a pitch matching that of the NAND strings.