Use of data latches in multi-phase programming of non-volatile memories
First Claim
1. A method of performing a programming operation in a non-volatile memory device having one or more memory cells each capable of storing N bits of data, where N is greater than or equal to one, and read/write circuitry connectable to the memory cells, the read/write circuitry including programming circuitry, bias circuitry to set bias conditions in the memory cells and one or more sets of latches each associated with a corresponding one of the memory cells to which the read/write circuitry is connected, the method comprising:
- applying a monotonically non-decreasing programming waveform from the programming circuitry to the memory cells;
concurrently with applying said programming waveform, setting bias conditions in the memory cells by said bias circuitry, wherein a first set of bias conditions is used during a first programming phase and a second set of bias conditions is used during a second programming phase; and
governing which of the programming phases is active by a first latch of each of said sets of latches.
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Abstract
A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
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Citations
17 Claims
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1. A method of performing a programming operation in a non-volatile memory device having one or more memory cells each capable of storing N bits of data, where N is greater than or equal to one, and read/write circuitry connectable to the memory cells, the read/write circuitry including programming circuitry, bias circuitry to set bias conditions in the memory cells and one or more sets of latches each associated with a corresponding one of the memory cells to which the read/write circuitry is connected, the method comprising:
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applying a monotonically non-decreasing programming waveform from the programming circuitry to the memory cells; concurrently with applying said programming waveform, setting bias conditions in the memory cells by said bias circuitry, wherein a first set of bias conditions is used during a first programming phase and a second set of bias conditions is used during a second programming phase; and governing which of the programming phases is active by a first latch of each of said sets of latches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification