Selectable-tap equalizer

• US 7,508,871 B2
• Filed: 10/12/2007
• Issued: 03/24/2009
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Stojanovic, Vladimir M, Zerbe, Jared L, Chen, Fred F
• Primary Examiner(s): Odom; Curtis B
• Application Number:
  US11/871,666
• Publication Number:
  US 20080049822A1
• Time in Patent Office: 529 Days
• Field of Search: 375229-236, 375346-350
• US Class Current: 375/229
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03025 using a two-tap delay line
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0058 detection of error based on equalizer tap values
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

Claims

1. A device comprising:

a transmit circuit to output a first data signal onto a first signal path during a first transmit interval;

a receive circuit to receive a second data signal from a second signal path during a first receive interval; and

an equalization circuit coupled to the first and second signal paths,

the equalization circuit to output a first equalization signal onto the first signal path during the first transmit interval, the first equalization signal having a signal level according to a plurality of data signals to be transmitted on the first signal path, and

the equalization circuit to output a second equalization signal onto the second signal path during the first receive interval, the second equalization signal having a signal level according to a plurality of data signals received on the second signal path.

2. The device of claim 1, wherein the transmit circuit includes an output driver to output the first data signal, and wherein the equalization circuit includes,

a buffer to store a plurality of data values that correspond to the plurality of data signals to be transmitted on the first signal path;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

a transmit equalization circuit to output the first equalization signal onto the first signal path, the first equalization signal having an amplitude according to the subset of data values.

3. The device of claim 2, wherein the buffer stores the plurality of data values that correspond to the plurality of data signals to be transmitted on the first signal path and another plurality of data values that correspond to a plurality of data signals that have been transmitted on the first signal path, wherein the select circuit selects the subset of data values from the plurality of data values and another plurality of data values.

4. The device of claim 2 further comprising a configuration circuit to store the select value and to output the select value.

5. The device of claim 1, wherein the equalization circuit includes,

a buffer to store a plurality of data values that correspond to the plurality of data signals received on the second signal path;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

a receive equalization circuit to output the second equalization signal onto the second signal path, the second equalization signal having an amplitude according to the subset of data values.

6. The device of claim 5, wherein the receive circuit includes a sampling circuit to receive the second data signal and the receive equalization circuit includes an output driver to output the second equalization signal.

7. The device of claim 5 further comprising a configuration circuit to store the select value and to output the select value.

8. The device of claim 1 wherein the equalization circuit includes,

a first buffer to store a first plurality of data values that correspond to the plurality of data signals to be transmitted on the first signal path;

and

a second buffer to store a second plurality of data values that correspond to the plurality of data signals received on the second signal path;

a select circuit coupled to the first and second buffers to select a subset of data values from the first and second plurality of values; and

a receive equalization circuit to output the second equalization signal onto the second signal path, the second equalization signal having an amplitude according to the subset of data values.

9. The device of claim 1, wherein the transmit circuit, receive circuit and equalization circuit are included in an integrated circuit.

10. A method comprising:

transmitting a first data signal, by a transmit circuit, on a first signal path during a first transmit interval;

transmitting a first equalization signal on the first signal path during the first transmit interval, the first equalization signal having a signal level according to data signals transmitted on the first signal path during a first time interval that precedes the first transmit interval;

receiving a second data signal from a second signal path during a first receive interval; and

transmitting a second equalization signal on the second signal path during the first receive interval, the second equalization signal having a signal level according to data signals received from the second signal path during a second time interval that precedes the first receive interval.

11. The method of claim 10 wherein transmitting a first equalization signal comprises:

storing a plurality of data values that correspond to the data signals transmitted on the first signal path; and

selecting a subset of data values from the plurality of data values according to a select value.

12. The method of claim 11 wherein transmitting a second equalization signal comprises:

storing a plurality of data values that correspond to the data signals received on the second signal path; and

selecting a subset of data values from the plurality of data values according to a select value.

13. The method of claim 11 further comprising storing the select value in a configuration circuit.

14. An integrated circuit device comprising:

a transmit circuit to output a first data signal onto a first signal path during a first transmit interval;

a receive circuit to receive a second data signal from a second signal path during a first receive interval;

a transmit equalization circuit to output a first equalization signal onto the first signal path during the first transmit interval, the first equalization signal having a signal level according to plurality of data signals to be transmitted on the first signal path, and

a receive equalization circuit to output a second equalization signal onto the second signal path during the first receive interval, the second equalization signal having a signal level according to a plurality of data signals received on the second signal path.

15. The integrated circuit device of claim 14, wherein

the transmit circuit includes a first output driver to output the first data signal, and

wherein the transmit equalization circuit includes,

a buffer to store a plurality of data values that correspond to the plurality of data signals to be transmitted on the first signal path;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

a second output driver to output the first equalization signal onto the first signal path, the first equalization signal having an amplitude according to the subset of data values.

16. The integrated circuit device of claim 14, wherein the receive equalization circuit includes,

a buffer to store a plurality of data values that correspond to the plurality of data signals received on the second signal path;

a select circuit coupled to the buffer to select a subset of data values from the plurality of data values according to a select value; and

an output driver to output the second equalization signal onto the second signal path, the second equalization signal having an amplitude according to the subset of data values.

17. The integrated circuit device of claim 14 wherein at least one of the first and second signal paths includes an impedance-altering structure to equalize the electrical lengths of the first and second signal paths.

18. The integrated circuit device of claim 14 further comprising a plurality of impedance-altering structures switchably coupled to at least one of the first and second signal paths.

19. The integrated circuit of claim 18 further comprising a configuration circuit coupled to the plurality of impedance-altering structures, the impedance-altering structures being switchably coupled to the at least one of the first and second signal paths in accordance with a setting of the configuration circuit.

20. The integrated circuit of claim 19 wherein the configuration circuit comprises a register to store a configuration value, the impedance-altering structures being selectively coupled to, or decoupled from, the at least one of the first and second signal path segments in accordance with the configuration value.