Multi-process descrambler

• US 7,508,942 B2
• Filed: 10/22/2003
• Issued: 03/24/2009
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Candelore, Brant L.
• Primary Examiner(s): Barron, Jr., Gilberto
• Assistant Examiner(s): Dinh, Minh
• Application Number:
  US10/691,170
• Publication Number:
  US 20040088552A1
• Time in Patent Office: 1,980 Days
• Field of Search: 380200-242, 380/284
• US Class Current: 380/239
• CPC Class Codes: H04N 21/4181 for conditional access
• CPC Class Codes: H04N 21/43607 Interfacing a plurality of external cards, e.g. through a DVB Common Interface [DVB-CI]
• CPC Class Codes: H04N 21/4405 involving video stream decryption
• CPC Class Codes: H04N 21/4408 involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
• CPC Class Codes: H04N 21/4623 Processing of entitlement messages, e.g. ECM [Entitlement Control Message] or EMM [Entitlement Management Message] arrangements for conditional access to broadcast information or to broadcast-related services H04H60/14
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

A descrambler integrated circuit (IC) is adapted to receive scrambled digital content and to descramble the scrambled digital content. According to one embodiment of the invention, the descrambler comprises a first process block, a second process block and a descrambler. The first process block is configured to encrypt a message using a unique, one-time programmable key to produce a first key. The second process block is configured to receive an encrypted second key and, using the first key, to decrypt the encrypted second key in order to recover the second key in a non-encrypted format. The descrambler is configured to descramble the scrambled digital content using the second key in the non-encrypted format and to produce digital content in a clear format.

Claims

1. A descrambler integrated circuit (IC) adapted to receive scrambled digital content, a message and an encrypted descrambling key, comprising:

a local memory to store a unique key;

a first process block to encrypt the message using the unique key to produce a key, the key being formed from a mating key generator being the message that comprises an identifier of a manufacturer of a digital device including the descrambler IC, a mating key sequence number, and an identifier of a supplier of the scrambled digital content, the supplier being one of a cable provider, a satellite-based provider, a terrestrial-based provider, and an Internet service provider;

a second process block using the key to decrypt the encrypted descrambling key and to recover a descrambling key; and

a descrambler using the descrambling key to descramble the scrambled digital content and to produce digital content in a clear format.

2. The descrambler IC of claim 1, wherein the unique key is loaded into the local memory during manufacture of the descrambler IC.

3. The descrambler IC of claim 1, wherein the second process block is a finite state machine.

4. The descrambler IC of claim 1, wherein the key is formed by encrypting the mating key generator using the unique key.

5. The descrambler IC of claim 1, wherein the mating key generator further comprises an identifier that identifies a provider of a system that enables transmission of the scrambled digital content and the mating key generator message to the descrambler IC.

6. The descrambler IC of claim 5, wherein the mating key generator further comprises an identifier that identifies a conditional access (CA) system provider over which the scrambled digital content and the mating key generator is transmitted.

7. The descrambler IC of claim 1, wherein the first process block and the second process block are logic operating in accordance with one of the following:

Data Encryption Standard (DES), Advanced Encryption Standard (AES), and Triple DES.

8. The descrambler IC of claim 1, wherein the unique key is a one-time programmable value that cannot be read or overwritten once programmed.

9. A descrambler integrated circuit (IC) adapted to receive scrambled digital content and to descramble the scrambled digital content, comprising:

a first process block to encrypt a message using a unique, one-time programmable key to produce a first key, the message includes a mating key generator being a message that comprises (i) an identifier of a manufacturer of a digital device employed with the descrambler IC, (ii) a mating key sequence number, and (iii) an identifier of a supplier of the scrambled digital content, the supplier being one of a cable provider, a satellite-based provider, a terrestrial-based provider, and an Internet service provider;

a second process block to receive an encrypted second key and, using the first key, to decrypt the encrypted second key in order to recover the second key in a non-encrypted format, the encrypted second key; and

a descrambler using the second key in the non-encrypted format to descramble the scrambled digital content and to produce digital content in a clear format.

10. The descrambler IC of claim 9, wherein the encrypted second key is an encrypted service key associated with at least one selected tier of service.

11. The descrambler IC of claim 9, wherein the encrypted second key is an encrypted descrambling key from a smart card in communication with the descrambler IC.

12. The descrambler IC of claim 9, wherein the mating key generator encrypted by the first process block using the unique key to produce a result being the first key.

13. The descrambler IC of claim 9, wherein the encrypted second key is the second key encrypted to a mating key being a value retrieved from a remote server using the mating key generator and a serial number of a digital device implemented with the descrambler IC.

14. A descrambler integrated circuit (IC) adapted to receive scrambled digital content, a message and an encrypted descrambling key, comprising:

a local memory to store a unique key;

a first process block controlled by a non-CPU based state machine to encrypt a message using the unique key to produce a key, the message being a mating key generator that comprises (i) a mating key sequence number, (ii) an identifier of a manufacturer of a digital device employed with the descrambler IC, and (iii) an identifier of a supplier of the scrambled digital content, the supplier being one of a cable provider, a satellite-based provider, a terrestrial-based provider, and an Internet service provider;

a second process block controlled by a non-CPU state machine using the key to decrypt the encrypted descrambling key to recover a descrambling key; and

a descrambler using the descrambling key to the descramble the scrambled digital content and to produce digital content in a clear format.

15. The descrambler IC of claim 14, wherein the unique key is loaded into the local memory during manufacture of the descrambler IC and cannot be read or overwritten once programmed.

16. The descrambler IC of claim 14, wherein the first process block and the second process block are logic operating in accordance with one of the following:

Data Encryption Standard (DES), Advanced Encryption Standard (AES), and Triple DES.