System level simulation models for hardware modules

• US 7,509,246 B1
• Filed: 06/09/2003
• Issued: 03/24/2009
• Est. Priority Date: 06/09/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Molson, Philippe, San, Tony, Fox, Jeffrey R.
• Primary Examiner(s): Rodriguez; Paul L
• Assistant Examiner(s): PIERRE LOUIS, ANDRE
• Application Number:
  US10/458,516
• Time in Patent Office: 2,115 Days
• Field of Search: 703/13, 717/135, 717/140
• US Class Current: 703/13
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Methods and apparatus automate creation of code for system level simulations from hardware representations, specifically RTL representations. In one approach, individual RTL hardware modules are analyzed to generate code for corresponding system level modules. This is accomplished by taking a mapped netlist for a register transfer level (RTL) representation of the hardware module and converting it to what can be termed a “system level netlist.” This system level netlist contains “system level instances” corresponding to “hardware cells” of the mapped netlist. A mapped netlist includes hardware cells corresponding to programmed hardware units of a target hardware device. The method generates corresponding functional representations (code for system level simulation) from these hardware cells. This functional representation is referred to herein as a system level instance. System level instances are generated for each of the hardware cells in a given hardware module.

Claims

1. A method of automatically generating a system level representation of a hardware module suitable for execution in a system-level simulator, the method comprising:

(a) receiving a mapped netlist of a hardware module which mapped netlist comprises hardware cells, each specifying one or more hardware functions to be implemented on a corresponding hardware unit of a target hardware device, the hardware cells collectively comprising a mapped netlist;

(b) accessing one or more un-parameterized system level units, each system level unit being a software class that represents generically one of said corresponding hardware units of the target hardware device;

(c) instantiating the un-parameterized system level units to create system level instances, each programmed to perform the hardware functions of one of said hardware cells, each system-level instance being a software object that is coded in a general-purpose language;

(d) creating a hardware implementation-independent system level netlist based on the mapped netlist using said system level instances, said system level netlist being distinct from said mapped netlist; and

(e) compiling the system level netlist to produce an executable version of the system level representation, said executable version being simulation code suitable for execution in a system-level simulator;

wherein the steps a-e is performed using one or more processor.

2. The method of claim 1, further comprising:

performing a system level simulation on the hardware module by executing the executable version of the system level representation in a system-level simulator.

3. The method of claim 1, wherein the hardware units correspond to one or more of logic elements, memory elements, and register elements provided on the target hardware device.

4. The method of claim 1, wherein the un-parameterized system level units are C++ classes.

5. The method of claim 1, wherein instantiating the un-parameterized system level units comprises specifying ports and logical functions for the un-parameterized system level units.

22. A method as recited in claim 1 further comprising:

automatically creating said system level instances from said hardware cells of said mapped netlist using a netlist converter.

6. A computer program product comprising a machine storage medium on which is provided program instructions for automatically generating a system level representation of a hardware module, when executed by a processor performs the steps of:

(a) receiving a mapped netlist of a hardware module which mapped netlist comprises hardware cells, each specifying one or more hardware functions to be implemented on a corresponding hardware unit of a target hardware device, the hardware cells collectively comprising a mapped netlist;

(b) accessing one or more un-parameterized system level units, each system level unit being a software class that represents generically one of said corresponding hardware units of the target hardware device;

(c) instantiating the un-parameterized system level units to create system level instances, each programmed to perform the hardware functions of one of said hardware cells, each system-level instance being a software object that is coded in a general-purpose language;

(d) creating a hardware implementation-independent system level netlist based on the mapped netlist using said system level instances, said system level netlist being distinct from said mapped netlist; and

(e) compiling the system level netlist to produce an executable version of the system level representation, said executable version being simulation code suitable for execution in a system-level simulator.

7. The computer program product of claim 6, further comprising code for performing a system level simulation on the hardware module by executing the system level representation.

8. The computer program product of claim 6, wherein the hardware units correspond to one or more of logic elements, memory elements, and register elements provided on the target hardware device.

9. The computer program product of claim 6, wherein the un-parameterized system level units are C++ classes.

10. The computer program product of claim 6, wherein the code for instantiating the un-parameterized system level units comprises code for specifying ports and logical functions for the un-parameterized system level units.

11. An apparatus for automatically generating a system level representation of a hardware module, the apparatus comprising:

memory;

one or more processors;

an electronic design automation tool embodied in said memory for compiling RTL representations of electronic designs comprising hardware modules;

a system level environment embodied in said memory for entering electronic designs and performing system level simulations of said electronic designs; and

a system level hardware development tool platform embodied in said memory for generating system level representations of the hardware modules, which system level representations can be executed in a system level simulation to simulate the behavior of the hardware modules,

wherein said system level hardware development tool platform generates the system level representations from mapped netlists of hardware modules which mapped netlists comprise hardware cells, each hardware cell specifying one or more hardware functions to be implemented on a corresponding hardware unit of a target hardware device, the hardware cells collectively defining one of said mapped netlists; and

wherein said system level hardware development tool platform generates the system level representations from mapped netlists of hardware modules by

(i) accessing one or more un-parameterized system level units, each system level unit being a software class that represents generically one of said corresponding hardware units of the target hardware device,

(ii) instantiating the un-parameterized system level units to create system level instances, each programmed to perform the hardware functions of one of said hardware cells, each system-level instance being a software object that is coded in a general-purpose language,

(iii) creating a hardware implementation-independent system level netlist based on the mapped netlist using said system level instances, said system level netlist being distinct from said mapped netlist, said system level netlist being embodied in said memory, and

(iv) compiling the system-level netlist to produce executable simulation code suitable for execution in a system-level simulator.

12. The apparatus of claim 11, wherein the electronic design automation tool comprises logic for synthesizing said electronic designs.

13. The apparatus of claim 11, wherein the electronic design automation tool comprises logic for programming said electronic designs onto target hardware devices.

14. The apparatus of claim 11, wherein the hardware units correspond to one or more of logic elements, memory elements, and register elements provided on the target hardware device.

15. The apparatus of claim 11, wherein the un-parameterized system level units are C++ classes.

16. The apparatus of claim 11, wherein the system level hardware development tool platform instantiates the un-parameterized system level units by specifying ports and logical functions for the un-parameterized system level units.

17. A method of automatically generating a system level representation of a hardware module, the method comprising:

(a) receiving a mapped netlist for a register transfer level (RTL) representation of the hardware module, which mapped netlist comprises hardware cells corresponding to programmed hardware units of a target hardware device;

(b) converting said mapped netlist to a hardware implementation-independent system level netlist comprising system level instances corresponding to the hardware cells, each system-level instance being a software object that is coded in a general-purpose language, wherein the system level netlist is based on the mapped netlist, said system level netlist being distinct from said mapped netlist; and

(c) compiling the system level netlist to produce an executable version of the system level representation, said executable version being simulation code suitable for execution in a system-level simulator;

wherein the steps a-c is performed using a processor.

18. A method of automatically generating a system level representation of a hardware module, the method comprising:

(a) receiving a register transfer level (RTL) representation of the hardware module;

(b) elaborating the RTL representation to produce a netlist;

(c) mapping the netlist to hardware units of a target hardware device, on which the hardware module may be programmed, to create hardware cells, each hardware cell specifying one or more hardware functions to be implemented on a corresponding hardware unit, the hardware cells collectively comprising a mapped netlist;

(d) accessing one or more un-parameterized system level units, each system level unit being a software class that represents generically one of said corresponding hardware units of the target hardware device;

(e) instantiating the un-parameterized system level units to create system level instances, each programmed to perform the hardware functions one of said hardware cells, each system-level instance being a software object that is coded in a general-purpose language;

(f) creating a hardware implementation-independent system level netlist based on the mapped netlist using said system level instances, said system level netlist being distinct from said mapped netlist; and

(g) compiling the system level netlist to produce an executable version of the system level representation, said executable version being simulation code suitable for execution in a system-level simulator;

wherein the steps a-g is performed using a processor.

19. The method of claim 18, further comprising synthesizing the netlist produced from the RTL representation.

20. The method of claim 18, wherein the RTL representation of the hardware module comprises hardware design language code.

21. An apparatus for automatically generating a system level representation of a hardware module, the apparatus comprising:

(a) means for receiving a register transfer level (RTL) representation of the hardware module;

(b) means for elaborating the RTL representation to produce a netlist;

(c) means for mapping the netlist to hardware units of a target hardware device, on which the hardware module may be programmed, to create hardware cells, each specifying one or more hardware functions to be implemented on a corresponding hardware unit, the hardware cells collectively comprising a mapped netlist;

(d) means for accessing one or more un-parameterized system level units, each system level unit being a software class that represents generically one of said corresponding hardware units of the target hardware device;

(e) means for instantiating the un-parameterized system level units to create system level instances, each programmed to perform the hardware functions of one of said hardware cells, each system-level instance being a software object that is coded in a general-purpose language;

(f) means for creating a hardware implementation-independent system level netlist based on the mapped netlist using said system level instances, said system level netlist being distinct from said mapped netlist, said system level netlist being embodied in memory of said apparatus; and

(g) means for compiling the system-level netlist to produce executable simulation code suitable for execution in a system-level simulator.