Fault-tolerant synchronisation device for a real-time computer network

• US 7,509,513 B2
• Filed: 12/20/2001
• Issued: 03/24/2009
• Est. Priority Date: 01/16/2001
• Status: Expired due to Term

• Current Assignee: Thales SA
• Original Assignee: Thales SA
• Inventors: Toillon, Patrice, Colas, Gerard
• Primary Examiner(s): CHEN, TSE W
• Application Number:
  US10/250,474
• Publication Number:
  US 20040078614A1
• Time in Patent Office: 2,651 Days
• Field of Search: 713/375, 713/400
• US Class Current: 713/375
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/18 using passive fault-masking of the redundant circuits error detection by comparing the output of redundant processing systems with continued operation after detection of the error G06F11/165

Abstract

Fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device is disclosed. Global scheduling of the real-time computer platform in the form of minor and major cycles is provided in order to reduce latency during sensor acquisition. The associated calculation and preparation of output to the actuator is provided in an integrated modular avionic (IMA) architecture. To achieve the foregoing, a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner is provided.

Claims

1. A method of synchronizing local real-time clocks of a plurality of computer components via synchronization units of each of said plurality of computer components communicating together comprising:

receiving a configuration signal from a local processor of a first computer component separate from a data transfer bus;

generating on differential lines one or more outbound synchronization pulses with dominant and recessive states for transmission over a synchronization bus common to the synchronization units;

receiving from said synchronization bus one or more inbound synchronization pulses;

performing quadruplex majority voting by eliminating synchronization pairs originating from a same synchronization unit;

synchronizing the local real-time clocks based upon any one of minor and major cycles;

implementing a multiple operation state control of a synchronization unit, wherein a transition from an Out of sync operating state to an In sync operating state is triggered by a sending of a first code Start_miF or of a second code Start_MAF, and a transition from the In sync operating state to the Out of sync operating state is triggered by a fault vote on three codes comprising Init_sync, Start_miF, and Start_MAF; and

resynchronizing a real-time clock synchronization signal for transmission to a second computer component based upon processing of said configuration signal and said one or more inbound synchronization signals.

2. The synchronization method of claim 1, wherein said synchronizing of the local real-time clocks is achieved by any one of minor and major cycles of multiple periods of the local real-time clocks.

3. The synchronization method of claim 2, wherein a ratio of the major cycle periods to that of the minor cycle is a value between 2 and 10000.

4. The synchronization method of claim 1, wherein said synchronizing of the local real-time clocks is based upon minor and major cycles of multiple periods.

5. The synchronization method of claim 4, wherein a ratio of the major cycle periods to that of the minor cycle is a value between 2 and 10000.

6. The synchronization method of claim 1, further comprising encoding four calibrated synchronization signals.