Test pattern compression for an integrated circuit test environment
First Claim
1. A computer-readable medium storing computer-executable instructions for causing a computer to perform acts comprising:
- generating symbolic expressions that are associated with scan cells of an integrated circuit design, the symbolic expressions being a function of input variables of a decompressor configured to input the input variables and concurrently output decompressed test pattern bits, the act of generating the symbolic expressions comprising simulating the decompressor;
generating a test cube having at least a portion of the scan cells assigned predetermined values;
formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions; and
solving the equations to obtain a compressed test pattern.
2 Assignments
0 Petitions
Accused Products
Abstract
A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
-
Citations
21 Claims
-
1. A computer-readable medium storing computer-executable instructions for causing a computer to perform acts comprising:
-
generating symbolic expressions that are associated with scan cells of an integrated circuit design, the symbolic expressions being a function of input variables of a decompressor configured to input the input variables and concurrently output decompressed test pattern bits, the act of generating the symbolic expressions comprising simulating the decompressor; generating a test cube having at least a portion of the scan cells assigned predetermined values; formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions; and solving the equations to obtain a compressed test pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A computer-readable medium comprising computer-executable instructions for causing a computer to perform the act of:
generating a compressed test pattern for testing an integrated circuit by using symbolic expressions associated with scan cells of the integrated circuit, the symbolic expressions including linear combinations of input variables that are to be applied to a decompressor configured to decompress the input variables into test pattern bits and configured to apply the test pattern bits to scan chains of the integrated circuit as the input variables are received. - View Dependent Claims (12, 13, 14, 15, 16, 17)
-
18. A method, comprising:
-
generating a compressed test pattern for testing an integrated circuit by using symbolic expressions associated with scan cells of the integrated circuit, the symbolic expressions including linear combinations of input variables that are to be applied to a decompressor configured to decompress the input variables into test pattern bits and configured to apply the test pattern bits to scan chains of the integrated circuit as the input variables are received; and storing the compressed test pattern. - View Dependent Claims (19, 20, 21)
-
Specification