Dynamic frequency scaling for JTAG communication

• US 7,509,549 B2
• Filed: 12/27/2006
• Issued: 03/24/2009
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Larson, Lee, Laurenti, Gilbert
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US11/616,673
• Publication Number:
  US 20080163017A1
• Time in Patent Office: 818 Days
• Field of Search: 714/726, 714/724, 714/38, 714/39, 714/701, 714/47, 714/48, 714/733, 714/734, 714/30
• US Class Current: 714/726
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence

Abstract

A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Claims

1. A system, comprising:

a system under test (SUT) comprising a control logic; and

testing logic coupled to said SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT;

wherein said control logic monitors a number of activated processors in a scan chain coupled to the control logic;

wherein, if said number of activated processors is reduced, the control logic dynamically decreases a frequency of said clock signal.

2. The system of claim 1, wherein said clock signal comprises a Joint Test Action Group (JTAG) clock signal.

3. The system of claim 1, wherein the communications between the testing logic and the SUT are for debugging software stored on the SUT.

4. The system of claim 1, wherein the control logic monitors said number of activated processors in the scan chain by monitoring the number of test access ports (TAPs) associated with the scan chain.

5. The system of claim 1, wherein a primary test access port (TAP) is associated with the control logic and a secondary TAP is associated with a processor, and wherein, if said scan chain comprises only the primary TAP and no activated secondary TAPs, the control logic decreases said frequency of the clock signal.

6. The system of claim 5, wherein, if said scan chain comprises the primary TAP and a secondary TAP, the control logic increases said frequency of the clock signal.

7. The system of claim 1, wherein the control logic periodically monitors the number of activated processors and wherein the control logic adjusts the frequency of the clock signal multiple times in accordance with said monitoring.

8. A device, comprising:

a storage comprising software code; and

a control logic adapted to receive a clock signal from a testing logic external to said device, said clock signal usable to facilitate the transmission of test signals between the control logic and said testing logic, said test signals usable to debug the software code;

wherein, if the control logic determines that a number of processors in a scan chain of the device has been reduced, the control logic dynamically decreases a frequency of said clock signal.

9. The device of claim 8, wherein said clock signal comprises a Joint Test Action Group (JTAG) clock signal.

10. The device of claim 8, wherein, if the control logic determines that a number of processor test access ports (TAPs) in the scan chain of the device has been reduced, the control logic decreases the frequency of said clock signal.

11. The device of claim 8, wherein a primary test access port (TAP) is associated with the control logic and a secondary TAP is associated with a processor, and wherein, if the scan chain comprises only the primary TAP and no secondary TAPs, the control logic decreases the frequency of the clock signal.

12. The device of claim 11, wherein, if said scan chain comprises the primary TAP and a secondary TAP, the control logic increases the frequency of the clock signal.

13. The device of claim 8, wherein the control logic comprises a first logic to monitor said number of processors and a clock divider, and wherein said clock divider adjusts said frequency of the clock signal using a signal provided by said first logic.

14. The device of claim 8, wherein the control logic decreases the frequency of the clock signal to a predetermined frequency preprogrammed into the device.

15. A method, comprising:

transferring a communication clock signal from a testing logic to a system under test (SUT) to facilitate communications between said testing logic and the SUT, said communications including test signals used to debug software stored on the SUT;

monitoring the number of activated processors in a scan chain of the SUT; and

adjusting a frequency of the communication clock signal in accordance with said number of activated processors.

16. The method of claim 15, wherein transferring said communication clock signal comprises using a Joint Test Action Group (JTAG) clock signal.

17. The method of claim 15, wherein monitoring said number of activated processors in the scan chain comprises monitoring a number of processor test access ports (TAPs) in said scan chain.

18. The method of claim 15, wherein a primary test access port (TAP) is associated with a control logic of the SUT and a secondary TAP is associated with a processor of the SUT, and wherein, if said scan chain comprises the primary TAP but no activated secondary TAPs, the method comprises reducing said frequency of the communication clock signal.

19. The method of claim 18, wherein, if said scan chain comprises the primary TAP and a secondary TAP, the method comprises increasing said frequency of the communication clock signal.

20. The method of claim 15, wherein adjusting said frequency comprises adjusting the frequency before the communication clock signal is transferred from the testing logic to the SUT.