Field effect transistor and method of its manufacture

• US 7,511,339 B2
• Filed: 07/30/2003
• Issued: 03/31/2009
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mo, Brian S., Sapp, Steven, Probst, Dean E., Chau, Duc, Bencuya, Izak
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US10/630,249
• Publication Number:
  US 20040145015A1
• Time in Patent Office: 2,071 Days
• Field of Search: 257229-341, 257510-513
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A field effect transistor comprising:

a semiconductor substrate having dopants of a first conductivity type;

a trench extending a predetermined depth into the semiconductor substrate, wherein a gate structure is formed inside the trench;

a doped well having dopants of a second conductivity type opposite to the first conductivity type and extending into the semiconductor substrate to form a well junction at a first depth;

a doped source region having dopants of the first conductivity type and extending into the semiconductor substrate to form a source junction at a second depth; and

a doped heavy body region having dopants of the second conductivity type and extending into the doped well to form a heavy body junction at a depth that is deeper than the source junction and shallower than the trench,

wherein the heavy body region forms an abrupt junction at the interface between the heavy body region having dopants of the second conductivity type and the doped well having dopants of the second conductivity type, such that, when voltage is applied to the transistor, a peak electric filed occurs near the area of the interface.

2. The field effect transistor of claim 1 wherein a location of the abrupt junction relative to the well junction is adjusted so that, when voltage is applied to the transistor, a peak electric field is spaced away from the trench in the semiconductor.

3. The field effect transistor of claim 1 wherein the doped well has a substantially flat bottom.

4. The field effect transistor of claim 1 wherein the trench has rounded top corners.

5. The field effect transistor of claim 1 wherein the trench has rounded bottom corners.

6. The field effect transistor of claim 1 wherein the trench has rounded top and bottom corners.

7. The field effect transistor of claim 1 wherein the heavy body comprises a heavily doped region formed by implanting dopants of the second conductivity type at an approximate location of the abrupt junction.

8. The field effect transistor of claim 1 wherein the trench is lined with a dielectric material and substantially filled with conductive material, wherein the conductive material substantially filling the trench is recessed relative to the surface of the substrate.

9. The field effect transistor of claim 1 wherein the substrate comprises a first highly doped region and a second doped region disposed above said first highly doped region, the second doped region having a lower doping concentration relative to the first highly doped region.

10. The field effect transistor of claim 9 further comprising a termination structure surrounding the transistor.

11. The field effect transistor of claim 10 wherein the termination structure comprises a doped region having dopants of the second conductivity type extending into the second doped region of the substrate to form a PN junction between the termination doped region and the second doped region of the substrate.

12. The field effect transistor of claim 10 wherein the termination structure comprises a trench.

13. The field effect transistor of claim 10 wherein the termination structure comprises a plurality of concentric trenches surrounding the transistor.

14. The field effect transistor of claim 12 wherein the termination trench extends to substantially the same depth as the transistor trench.

15. The field effect transistor of claim 9 wherein the second doped region of the substrate has an initial thickness of less than 10 μ

m.

16. The field effect transistor of claim 9 wherein the doped well extends into the second doped region of the substrate such that the resulting thickness of the second doped region of the substrate is less than 3 μ

m.

17. The field effect transistor of claim 9 wherein the doped well extends into the second doped region of the substrate such that the resulting thickness of the second doped region of the substrate is approximately 1 μ

m.

18. The field effect transistor of claim 1 wherein the depth of the doped well ranges from approximately 1 μ

m to 3 μ

m.

19. The field effect transistor of claim 1 wherein the depth of the doped heavy body ranges from approximately 0.4 μ

m to 1.5 μ

m.

20. The field effect transistor of claim 1 wherein a distance between a bottom of the doped heavy body to the doped well junction ranges from approximately 0.5 μ

m to 1.5 μ

m.

21. The field effect transistor of claim 1 wherein a distance between a bottom of the doped heavy body to the doped well junction is less than approximately 0.5 μ

m.

22. A field effect transistor comprising:

a semiconductor substrate having dopants of a first conductivity type;

a plurality of gate-forming trenches arranged substantially parallel to each other, each trench extending to a first depth into said substrate, the space between adjacent trenches defining a contact area;

a doped well having dopants of a second conductivity type opposite to the first conductivity type and extending into the semiconductor substrate to form a well junction with the substrate;

a doped source region having dopants of the first conductivity type forming a source junction inside the doped well;

a heavy body having dopants of the second conductivity type and extending into the doped well to a second depth that is deeper than the source junction; and

heavy body contact regions defined at the surface of the semiconductor substrate along the length of the contact area,

wherein the heavy body forms an abrupt junction at the interface between the heavy body region having dopants of the second conductivity type and the doped well having dopants of the second conductivity type, such that, when voltage is applied to the transistor, a peak electric filed occurs near the area of the interface.

23. The field effect transistor of claim 22, wherein said doped well has a substantially flat bottom.

24. The field effect transistor of claim 22 wherein a location of the abrupt junction relative to the well junction at the second depth is adjusted so that, when voltage is applied to the transistor, a peak electric field is spaced away from the plurality of gate-forming trenches.

25. The field effect transistor of claim 22 wherein said doped well has a depth less than the first depth of the gate-forming trenches.

26. The field effect transistor of claim 22 wherein each said gate-forming trench has rounded top corners.

27. The field effect transistor of claim 22 wherein each said gate-forming trench has rounded bottom corners.

28. The field effect transistor of claim 22 wherein each said gate-forming trench has rounded top and bottom corners.

29. The field effect transistor of claim 22 further comprising a deep doped region having dopants of the second conductivity type, the deep doped region extending into the substrate to a depth greater than the first depth of the plurality of gate-forming trenches.

30. The field effect transistor of claim 29 wherein the deep doped region forms a PN junction diode with the substrate.

31. The field effect transistor of claim 29 wherein the deep doped region forms a field termination structure surrounding the periphery of the plurality of gate-forming trenches.

32. The field effect transistor of claim 31 further comprising:

a layer of dielectric material formed over the deep doped region; and

a layer of conductive material formed on top of the layer of dielectric material.

33. The field effect transistor of claim 22 further comprising a field termination structure comprising a trench substantially surrounding the plurality of gate-forming trenches.

34. The field effect transistor of claim 33 wherein said field termination structure comprises a plurality of concentrically arranged trenches.

35. The field effect transistor of claim 22 wherein the heavy body forms a continuous doped region along substantially the entire length of said contact area.

36. The field effect transistor of claim 22 wherein said doped source region extends along the length of the trench.

37. The field effect transistor of claim 36 further comprising a source contact region defined at the surface of the semiconductor substrate and configured to contact the doped source region.

38. The field effect transistor of claim 36 further comprising a plurality of source contact regions disposed along the length of the contact area in an alternating fashion with the plurality of heavy body contact regions.

39. The field effect transistor of claim 22 wherein between a pair of adjacent trenches a plurality of doped source regions are positioned on opposite sides of each trench, and wherein the heavy body is bounded by the pair of adjacent trenches and the doped source regions.

40. The field effect transistor of claim 22 wherein between a pair of adjacent trenches, the heavy body extends continuously parallel to the longitudinal axis of the trenches.

41. The field effect transistor of claim 22 further comprising:

a layer of dielectric material lining inside walls of each of said plurality of gate-forming trenches; and

a layer of conductive material substantially filling the gate-forming trenches.

42. The field effect transistor of claim 41 wherein the layer of conductive material comprises polysilicon.

43. The field effect transistor of claim 41 wherein the top surface of the layer of conductive material substantially filling the gate-forming trenches is recessed relative to the top surface of the semiconductor substrate.

44. The field effect transistor of claim 22 wherein the substrate comprises a first highly doped region and a second doped region disposed above said first highly doped region, the second doped region having a lower doping concentration relative to the first highly doped region.

45. The field effect transistor of claim 44 wherein the second doped region of the substrate has an initial thickness of less than 10 μ

m.

46. The field effect transistor of claim 44 wherein the doped well extends into the second doped region of the substrate such that the resulting thickness of the second doped region of the substrate is less than 3 μ

m.

47. The field effect transistor of claim 44 wherein the doped well extends into the second doped region of the substrate such that the resulting thickness of the second doped region of the substrate is approximately 1 μ

m.

48. The field effect transistor of claim 22 wherein the depth of the doped well ranges from approximately 1 μ

m to 3 μ

m.

49. The field effect transistor of claim 22 wherein the depth of the doped heavy body ranges from approximately 0.4 μ

m to 1.5 μ

m.

50. The field effect transistor of claim 22 wherein a distance between a bottom of the doped heavy body to the doped well junction ranges from approximately 0.5 μ

m to 1.5 μ

m.

51. The field effect transistor of claim 22 wherein a distance between a bottom of the doped heavy body to the doped well junction is less than approximately 0.5 μ

m.