Rail Schottky device and method of making

• US 7,511,352 B2
• Filed: 05/19/2003
• Issued: 03/31/2009
• Est. Priority Date: 05/19/2003
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Vyvoda, Michael A.
• Primary Examiner(s): Warren; Matthew E
• Application Number:
  US10/440,882
• Publication Number:
  US 20040232509A1
• Time in Patent Office: 2,143 Days
• Field of Search: 257/209, 257/473, 257/481, 257/485, 257/486, 257/530, 257/910, 257/594, 257/E23.147, 257/E27.05, 257/E29.338, 257/E31.065, 438/131, 438/600
• US Class Current: 257/473
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are “rightside-up” with antifuse over the metal, and those on even levels are “upside down” with metal over the antifuse. Both antifuses are preferably grown oxides.

Claims

1. A nonvolatile memory array comprising:

a first memory cell comprising portions of a first-type Schottky diode; and

a second memory cell comprising portions of a second-type Schottky diode wherein;

portions of the first-type Schottky diode comprise a first metal and the portions of the second-type Schottky diode comprise a second metal different from the first metal.

2. The memory array of claim 1 wherein the first metal is a silicide.

3. The memory array of claim 1 wherein the second metal does not reduce oxides.

4. The memory array of claim 3 wherein the second metal does not reduce silicon oxide.

5. The memory array of claim 1 wherein:

the portions of the first-type Schottky diode comprise a first antifuse; and

the portions of the second-type Schottky diode comprise a second antifuse.

6. The memory array of claim 5 wherein the first antifuses are grown.

7. The memory array of claim 6 wherein:

the first antifuse is over the first metal in the first-type Schottky diode; and

the second metal is over the second antifuse in the second-type Schottky diode.

8. The memory array of claim 6 wherein

the portions of second-type Schottky diode further comprise a second semiconductor and

the Schottky barrier height between the second semiconductor and the second metal is between 0.3 and 0.75 electron volts.

9. The memory array of claim 8 wherein the second metal is titanium nitride, tantalum nitride, or tungsten nitride.

10. The memory array of claim 9 wherein the second metal is titanium nitride.

11. The memory array of claim 10 wherein the first metal is cobalt silicide.

12. The memory array of claim 9 wherein the memory array is a monolithic three dimensional memory array.

13. The memory array of claim 12 wherein the monolithic three dimensional memory array comprises:

a first memory level over a substrate; and

a second memory level over the first memory level, wherein the first memory level comprises the first memory cell and the second memory level comprises the second memory cell.

14. A monolithic three dimensional memory array comprising:

a plurality of incipient first-type Schottky diodes, each comprising a first metal which is a silicide; and

a plurality of incipient second-type Schottky diodes, each comprising a second metal different from the first metal.

15. The memory array of claim 14 wherein each of the plurality of incipient first-type Schottky diodes further comprises:

a first layer of lightly doped or intrinsic silicon; and

a first antifuse, wherein the first metal and first silicon layer are separated by the first antifuse.

16. The memory array of claim 15 wherein the first antifuses are grown.

17. The memory array of claim 16 wherein each of the plurality of incipient second-type Schottky diodes further comprises:

a second layer of lightly doped or intrinsic silicon; and

a second antifuse, wherein the second silicon layer and the second metal are separated by the second antifuse.

18. The memory array of claim 17, further comprising:

a plurality of substantially parallel first rails extending in a first direction above a substrate; and

a plurality of substantially parallel second rails extending in a second direction, different from the first direction, over the first rails;

wherein;

the first rails comprise the first metal of the plurality of incipient first-type Schottky diodes; and

the second rails comprise the first layers of lightly doped intrinsic silicon of the plurality of incipient first-type Schottky diodes.

19. The memory array of claim 18, further comprising:

a plurality of substantially parallel third rails extending in the first direction, over the second rails;

wherein;

the second rails comprise the second layers of lightly doped or intrinsic silicon of the plurality of incipient second-type Schottky diodes; and

the third rails comprise the second metal of the plurality of incipient second-type Schottky diodes.

20. The memory array of claim 19 wherein the first rails further comprise the first antifuses of the plurality of incipient first-type Schottky diodes.

21. The memory array of claim 20 wherein the second rails further comprise the second antifuses of the plurality of incipient second-type Schottky diodes.

22. The memory array of claim 21 wherein the first metal is cobalt silicide.

23. The memory array of claim 22 wherein the second metal is titanium nitride, tantalum nitride, or tungsten nitride.

24. The memory array of claim 23 wherein the second layers of lightly doped or intrinsic silicon comprise polysilicon.

25. The memory array of claim 24 wherein the first layers of lightly doped or intrinsic silicon comprise polysilicon.

26. The memory array of claim 25 wherein the first layers of silicon comprise lightly doped n-type silicon.

27. The memory array of claim 25 wherein the first layers of silicon comprise intrinsic silicon.

28. The memory array of claim 25 wherein at least one antifuse comprises silicon oxide.

29. A memory cell comprising:

a layer of lightly doped or intrinsic silicon;

an antifuse in contact with the silicon; and

a layer of titanium nitride in contact with the antifuse,

wherein the antifuse is above the silicon and the titanium nitride is above the antifuse.

30. A method for making a monolithic three dimensional memory array comprising:

forming a plurality of substantially parallel first rails comprising first metal layers adjacent to first antifuses;

forming a plurality of substantially parallel second rails over the first rails, said second rails comprising;

first layers of lightly doped or intrinsic silicon; and

second layers of lightly doped or intrinsic silicon over the first silicon layers; and

forming a plurality of substantially parallel third rails over the second rails, said third rails comprising second metal layers adjacent to second antifuses, wherein the second metal of the second metal layers is different from the first metal of the first metal layers.

31. The method of claim 30 wherein the first metal is a silicide.

32. The method of claim 31 wherein the first metal layers and first layer of lightly doped or intrinsic silicon form incipient first-type Schottky diodes separated by the first antifuses.

33. The method of claim 32 wherein the second layers of lightly doped or intrinsic silicon and the second metal layers form incipient second-type Schottky diodes separated by the second antifuses.

34. The method of claim 33 wherein the first antifuses are grown.

35. A monolithic three dimensional memory array formed over a substrate comprising odd and even levels of memory above a substrate, wherein:

odd memory levels comprise portions of first-type Schottky diodes comprising a first metal; and

even memory levels comprise portions of second-type Schottky diodes comprising a second metal different from the first metal.

36. The monolithic three dimensional memory array of claim 35 wherein

the first metal is a silicide;

and

the second metal is titanium nitride, tantalum nitride, or tungsten nitride.

37. The monolithic three dimensional memory array of claim 36 wherein, when the portions of first-type Schottky diodes function as Schottky diodes, current flows substantially up in a vertical direction away from the substrate.

38. The monolithic three dimensional memory array of claim 37 wherein, when the portions of second-type Schottky diodes function as Schottky diodes, current flows substantially down in a vertical direction toward the substrate.

39. A memory array comprising:

portions of a first-type Schottky diode comprising a first semiconductor portion over a first metal portion, the first semiconductor portion and first metal portions separated by a first antifuse; and

portions of a second-type Schottky diode comprising a second metal portion over a second semiconductor portion, the second metal portion and the second semiconductor portion separated by a second antifuse,

wherein both antifuses are grown,

wherein the array comprises a monolithic three dimensional memory array,

wherein the first metal is different from the second metal.

40. A memory array comprising:

a plurality of Schottky diodes or incipient Schottky diodes; and

a vertical interconnect having a sidewall with a stair-step profile.

41. The memory array of claim 40 wherein the plurality of Schottky diodes or incipient Schottky diodes are vertically oriented.

42. The memory array of claim 41 wherein the memory array is a monolithic three dimensional memory array.

43. The memory array of claim 41 wherein the plurality of Schottky diodes or incipient Schottky diodes comprises portions of first-type Schottky diodes and portions of second-type Schottky diodes,

the first-type Schottky diodes comprising first semiconductor portions over first metal portions;

and

the second-type Schottky diodes comprising second metal portions over second semiconductor portions.

44. The memory array of claim 43 wherein

the first metal portions comprise a first metal,

the second metal portions comprise a second metal, and

the first metal is different from the second metal.

45. The memory array of claim 44 wherein the memory array is a monolithic three dimensional memory array.