Surface mountable direct chip attach device and method including integral integrated circuit

• US 7,511,379 B1
• Filed: 03/23/2006
• Issued: 03/31/2009
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Flint, D. Michael Jr.
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Nikmanesh; Seahvosh J
• Application Number:
  US11/389,412
• Time in Patent Office: 1,104 Days
• Field of Search: 257/E23.001, 257/E23.002, 257/E23.011, 257/E23.141, 257/E23.169, 257/E23.174, 257/E23.175
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A surface mountable chip comprises a semiconductor substrate having IC devices formed thereon and also vertically exposed electrical contacts formed as part of the IC fabrication substrate. Metallization lines electrically connect the IC devices with the contacts. The inventor also contemplates wafers having electrical connection vias in place on the wafers in preparation as a product for further fabrication. A method embodiment of the invention describes methods of fabricating such surface mountable chips.

Claims

1. A wafer substrate for use in the construction of a plurality of integrated leadless chip carriers, the substrate comprising:

a semiconductor wafer having a plurality of integrated circuit regions divided by a plurality of saw streets;

each integrated circuit region having edge portions that extend into the saw streets; and

vias formed in the edge portions and arranged so that at least a portion of the vias extend into the saw street, the vias filled with a conductive material to form edge contacts that do not extend completely through the wafer and configured such that upper portions of the edge contacts comprise stacked metallization layers formed on top of the conductive material.

2. The wafer substrate of claim 1 wherein the edge contacts include upper surfaces that are substantially circular in shape.

3. The wafer substrate of claim 1 wherein the edge contacts include upper surfaces that are substantially rectangular in shape.

4. The wafer substrate of claim 1 wherein integrated circuits are formed on a surface of the integrated circuit regions and electrically connected to the edge contacts.

5. The wafer substrate of claim 1 wherein the vias that extend in to the saw streets extend completely across the saw streets joining with the vias associated with adjacent integrated circuit regions.