Semiconductor memory device

• US 7,511,985 B2
• Filed: 04/17/2007
• Issued: 03/31/2009
• Est. Priority Date: 05/18/2006
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yamagata, Satoru, Sato, Shinichi, Horii, Shinji
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): Nguyen, Hien N
• Application Number:
  US11/785,311
• Publication Number:
  US 20070285972A1
• Time in Patent Office: 714 Days
• Field of Search: 365/148, 365/158, 365/171, 365/173
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.

Claims

1. A semiconductor memory device comprising:

a memory cell array having a plurality of memory cells arranged in rows and columns, each memory cell including a variable resistor element of a two-port structure capable of storing a data by shifting an electric resistance from a first state to a second state when a first writing voltage is applied to both ends of the variable resistor element and shifting the electric resistance from the second state to the first state when a second writing voltage is applied to both ends of the variable resistor element, and a selecting transistor connected at either its source or drain to one end of the variable resistor element, wherein

the memory cell has such a writing time characteristic that a second writing time required for shifting the electric resistance from the second state to the first state by applying the second writing voltage is longer than a first writing time required for shifting the electric resistance from the first state to the second state by applying the first writing voltage,

a second number of the memory cells subjected at once to a second writing action of shifting the electric resistance from the second state to the first state is greater than a first number of the memory cells subjected at once to a first writing action of shifting the electric resistance from the first state to the second state when some or entire of the memory cells in the memory cell array are selected, and

at least the second number of the memory cells is two or more between the first number and the second number of the memory cells.

2. The semiconductor memory device according to claim 1, wherein

a memory cell number rate determined by dividing the second number of the memory cells by the first number of the memory cells is set equal to or greater than a writing time rate determined by dividing the second writing time by the first writing time.

3. The semiconductor memory device according to claim 1, wherein

each of the first number of the memory cells and the second number of the memory cells is two or more.

4. The semiconductor memory device according to claim 1, wherein

an absolute value of the first writing voltage is greater than an absolute value of the second writing voltage.

5. The semiconductor memory device according to claim 4, wherein

the memory cell array includes a number of word lines extending along the rows and a number of bit lines extending along the columns, a gate of the selecting transistor in each of the memory cells arranged along one row is connected with a common word line while the variable resistor element in each of the memory cells arranged along one column is connected at the other end not connected to either the source or drain of the selecting transistor with the common bit line or either the source or drain of the selecting transistor not connected to one end of the variable resistor element is connected with the common bit line,

the selecting transistor is an N channel MOSFET, and

a positive voltage based on a level at either the source or drain of the selecting transistor not connected to one end of the variable resistor element in the memory cell to be written is applied to the other end of the variable resistor element not connected to either the source or drain of the selecting transistor in the memory cell to be written when the first writing voltage is applied to the memory cell to be written.

6. The semiconductor memory device according to claim 5, wherein

the first writing voltage and the second writing voltage are different to each other in the polarity, and

a negative voltage based on a level at either the source or drain of the selecting transistor not connected to one end of the variable resistor element in the memory cell to be written is applied to the other end of the variable resistor element not connected to either the source or drain of the selecting transistor in the memory cell to be written when the second writing voltage is applied to the memory cell to be written.

7. The semiconductor memory device according to claim 1, wherein

the first writing action is preliminarily conducted for setting the electric resistance to the second state before the memory cells to be written are subjected simultaneously to the second writing action based on a writing control procedure provided in advance.

8. The semiconductor memory device according to claim 7, wherein

the second number of the memory cells to be subjected at once to the second writing action is subjected to the reading action for retrieving the memory cells of which the electric resistance is not at the second state before the first writing action is preliminarily conducted, and the retrieved memory cells are preliminarily subjected to the first writing action based on a writing control procedure provided in advance.