Memory unit
First Claim
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1. A memory unit, comprising:
- a first load unit, having a first end coupled to a first voltage, and a second end coupled to a first contact;
a second load unit, having a first end coupled to the first voltage, and a second end coupled to a second contact;
a first metal-oxide-semiconductor (MOS) transistor, having a first end coupled to the first contact, a second end coupled to a second voltage, and a gate coupled to the second contact;
a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a gate coupled to the first contact;
a first non-volatile device having a split-gate structure, and having a control gate coupled to a first control bias voltage, a select gate coupled to a first select bias voltage, a first end coupled to the first contact, and a second end coupled to a first bit line; and
a second non-volatile device having a split-gate structure, and having a control gate coupled to a second control bias voltage, a select gate coupled to a second select bias voltage, a first end coupled to the second contact, and a second end coupled to a second bit line.
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Abstract
A memory unit is provided herein. The present invention utilizes two non-volatile devices having a split gate structure to save a logic state of the memory unit. Thus, even when a power supply for the memory unit is shut down, the non-volatile devices can still save the logic state. The memory unit not only has the advantage of high speed operation of a static random access memory, but also functions as a non-volatile memory for saving data.
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Citations
10 Claims
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1. A memory unit, comprising:
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a first load unit, having a first end coupled to a first voltage, and a second end coupled to a first contact; a second load unit, having a first end coupled to the first voltage, and a second end coupled to a second contact; a first metal-oxide-semiconductor (MOS) transistor, having a first end coupled to the first contact, a second end coupled to a second voltage, and a gate coupled to the second contact; a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a gate coupled to the first contact; a first non-volatile device having a split-gate structure, and having a control gate coupled to a first control bias voltage, a select gate coupled to a first select bias voltage, a first end coupled to the first contact, and a second end coupled to a first bit line; and a second non-volatile device having a split-gate structure, and having a control gate coupled to a second control bias voltage, a select gate coupled to a second select bias voltage, a first end coupled to the second contact, and a second end coupled to a second bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification