Apparatus and method for generating a tracking error signal in an optical disc drive

• US 7,512,043 B2
• Filed: 07/12/2005
• Issued: 03/31/2009
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: He, Wei-Hung
• Primary Examiner(s): Young; Wayne R
• Assistant Examiner(s): SIMPSON, LIXI CHOW
• Application Number:
  US11/160,820
• Publication Number:
  US 20060007807A1
• Time in Patent Office: 1,358 Days
• Field of Search: None
• US Class Current: 369/44.34
• CPC Class Codes: G11B 7/0906 Differential phase difference systems

Abstract

The present invention discloses an apparatus and method for generating a tracking error signal in an optical disc drive. The method includes: receiving a first and a second analog signals; converting the first and the second analog signals into a first and a second digital signals respectively; delaying the first and second digital signals to generate a first and a second delay signals respectively; generating the tracking error signal according to the first and second digital signals and the first and second delay signals.

Claims

1. An apparatus for generating a tracking error signal, the apparatus comprising:

an optical sense module for generating a first analog signal and a second analog signal according to the signal reflected from an optical disc;

an ADC (Analog-to-Digital Converter) module coupled to the optical sense module for translating the first and second analog signals into a first and a second digital signals respectively;

a delay module coupled to the ADC module for delaying the first and second digital signals to generate a first and a second delay signals respectively; and

a signal generation module coupled to the ADC module and the delay module for generating the tracking error signal according to the first and second digital signals and the first and second delay signals, the signal generation module comprising;

a digital logic module for generating a first control signal and a second control signal according to the first and second digital signals and the first and second delay signals;

wherein the digital logic module generates the tracking error signal according to the first and the second control signals, and the digital logic module enables the first or the second control signal when a value of one of the first and second digital signals and the first and second delay signals is different from values of the others of the first and second digital signals and the first and second delay signals.

2. The apparatus of claim 1, wherein the signal generation module further comprises:

a charge pump coupled to the digital logic module for generating the tracking error signal according to the first and second control signals.

3. The apparatus of claim 2, wherein the charge pump raises a level of the tracking error signal when the first control signal is enabled, and lowers the level of the tracking error signal when the second control signal is enabled.

4. The apparatus of claim 1, wherein the digital logic module enables the first control signal when a value of the first digital signal is different from values of the first and second delay signals and the second digital signal.

5. The apparatus of claim 1, wherein the digital logic module enables the second control signal when a value of the second digital signal is different from values of the first and second delay signals and the first digital signal.

6. The apparatus of claim 1, wherein the digital logic module enables the second control signal when a value of the first delay signal is different from values of the first and second digital signals and the second delay signal.

7. The apparatus of claim 1, wherein the digital logic module enables the first control signal when a value of the second delay signal is different from values of the first and second digital signals and the first delay signal.

8. The apparatus of claim 1, wherein the ADC module is a 1-bit ADC module.

9. The apparatus of claim 1, wherein the delay module delays the first and second digital signals two times of the sampling period of the ADC module to generate the first and second delay signals respectively.

10. The apparatus of claim 1 further comprising:

a frequency translation module for outputting a reference clock to the ADC module, the delay module and the signal generation module.

11. The apparatus of claim 10, wherein the frequency translation module is a PLL (Phase Locked Loop) circuit.

12. A method for generating a tracking error signal, the method comprising the following steps:

generating a first analog signal and a second analog signal according to the signals reflected from an optical disk;

translating the first and second analog signals into a first and a second digital signals respectively;

delaying the first and second digital signals to generate a first and a second delay signals respectively;

generating a first and a second control signals according to the first and second digital signals and the first and second delay signals; and

generating the tracking error signal according to the first and second control signals;

wherein the first or the second control signal is enabled when a value of one of the first and second digital signals and the first and second delay signals is different from values of the others of the first and second digital signals and the first and second delay signals.

13. The method of claim 12, wherein the first control signal is enabled when a value of the first digital signal is different from values of the first and second delay signals and the second digital signal.

14. The method of claim 12, wherein the second control signal is enabled when a value of the second digital signal is different from values of the first and second delay signals and the first digital signal.

15. The method of claim 12, wherein the second control signal is enabled when a value of the first delay signal is different from values of the first and second digital signals and the second delay signal.

16. The method of claim 12, wherein the first control signal is enabled when a value of the second delay signal is different from values of the first and second digital signals and the first delay signal.

17. The method of claim 12, wherein a level of the tracking error signal is raised when the first control signal is enabled, and the level of the tracking error signal is lowered when the second control signal is enabled.

18. The method of claim 12, wherein the first and second digital signals are 1-bit digital signals.

19. The method of claim 12, wherein the first and second analog signals are converted into the first and second digital signals in a sampling period of Ts, and the first and second digital signals are delayed 2Ts to generate the first and second delay signals respectively.