GPS RF front end IC with programmable frequency synthesizer for use in wireless phones

• US 7,512,385 B2
• Filed: 06/06/2005
• Issued: 03/31/2009
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Dubash, Noshir Behli, Zhang, Tao, Tso, Robert
• Primary Examiner(s): Smith; Creighton H
• Application Number:
  US11/149,436
• Publication Number:
  US 20060040631A1
• Time in Patent Office: 1,394 Days
• Field of Search: 455/118, 455/91, 455/95, 455/112, 455/260, 455/264, 455/262, 331/4
• US Class Current: 455/118
• CPC Class Codes: G01S 19/36 relating to the receiver frond end

Abstract

A GPS RF Front End IC containing a Programmable Frequency Synthesizer is disclosed. The GPS RF front end IC having a programmable frequency synthesizer allows a relatively fixed internal frequency plan while able to use a number of different reference frequencies provided by the host platform, which can be a wireless phone, or other such device, which can provide an accurate reference frequency signal.

Claims

1. A method for synthesizing a plurality of oscillator signals in a GPS RF Front End integrated within a wireless mobile, comprising the steps of:

producing a Local Oscillator (LO) signal with a Voltage Controlled Oscillator (VCO);

dividing the LO signal by a predetermined value of a first counter means that is coupled to the VCO to obtain a second signal with a frequency of LO divided by the predetermined value and results in a second signal;

dividing the LO signal by a second predetermined value generated by a second fixed counter means that result in a third signal, where the second fixed counter means has a first divide-by-N counter having multiple outputs;

dividing one of the first divide-by-N outputs by a second divide-by-N counter; and

comparing a phase and a frequency of the outputs of a first programmable count-down counter that is coupled to the second divide-by-N counter and the second programmable count-down counter, with a Phase Frequency Signal Detector where a reference frequency is also coupled to the second programmable count-down counter.

2. The method of claim 1, wherein the producing the Local Oscillator signal produces a (LO) signal with a frequency of approximately 1566 Mhz.

3. The method of claim 1, wherein the predetermined value is 41.

4. The method of claim 1, wherein the second predetermined value is 31-and 8/9ths that results in the third signal with a frequency of 9/7 of the second signal.

5. The method of claim 1, wherein the first counter means further comprises:

dividing the value of the first counter means with a divide-by-¾

counter having a divide-by-¾

output; and

dividing the divide-by-3 output with a divide-by-11 counter, wherein LO signal, the output of the divide-by-¾

, and the output of divide-by-11 counter assist in the generation of a select control signal to determine the divide ration of the divide-by-¾

counter.

6. The method of claim 1, wherein the first counter means, further comprise:

producing four quadrant signals each with a frequency of LO/4 with a divide-by-4 counter.

7. A method for synthesizing a plurality of oscillator signals in a GPS RE Front End integrated in a wireless device, comprising the steps of:

producing a first oscillator signal in the wireless device;

dividing the frequency of the first oscillator signal in the wireless device;

dividing the frequency of the first oscillator signal by more than one counter that results in more than one output used by a GPS receiver; and

comparing the phase and frequency of the outputs with a phase frequency signal detector to generate an output oscillator signal used by the wireless device.

8. The method of claim 7, wherein the oscillator signal has a frequency of approximately 1566 MHz.

9. The method of claim 7, includes:

dividing the frequency of the oscillator signal by a predetermined value of one of the more than one counters.

10. The method of claim 9, wherein the predetermined value is 41.

11. The method of claim 9, includes,

dividing the frequency of the oscillator signal by a second predetermined value of another one of the counters resulting in a second signal to generate the output oscillator signal.

12. The method of claim 11, further includes

generating the output oscillator signal with a frequency of 9/7th of the second signal when the predetermined value is 31 and 8/9ths.