Digital memory
First Claim
1. A memory configuration for use in a computer system, the memory comprising:
- a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; and
a data memory having a plurality of word lines of predetermined length,each of the said address decoders being activatable to select one of the plurality of word lines;
the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address; and
wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; and
wherein each address decoder identifier has an equal number of bits set to the first selectable state and the means to receive an input address is configured to receive addresses containing a predetermined number of bits set to the first selectable state.
1 Assignment
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Accused Products
Abstract
A memory configuration for use in a computer system includes a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states. A data memory having a plurality of word lines of predetermined length, is also included in each of the address decoders and is activatable to select one of the plurality of word lines. The address decoders receive an input address having a predetermined number of bits and compare the identifier of an address decoder with the input address wherein the memory further activates an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.
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Citations
31 Claims
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1. A memory configuration for use in a computer system, the memory comprising:
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a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address; and wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; and wherein each address decoder identifier has an equal number of bits set to the first selectable state and the means to receive an input address is configured to receive addresses containing a predetermined number of bits set to the first selectable state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A neural network memory configuration for use in a computer system, the memory comprising:
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a plurality of address decoder neurons each of which is connected to a predetermined number of input neurons; a data memory having a plurality data neurons, each of the said address decoder neurons being activatable to select some of the plurality of data neurons; the address decoder neurons including means to receive a signal representing a firing of an input neuron to which it is connected; and wherein an address decoder neuron comprises means to activate data neurons if firing signals are received from at least a predetermined minimum number of input neurons to which the address decoder neuron is connected.
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14. A method for operating a memory for use in a computer system, the memory comprising:
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a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; wherein an input address having a predetermined number of bits is input to the address decoder, the identifier of an address decoder is compared with the input address and address decoders are activated if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; wherein each address decoder identifier has an equal number of bits set to the first selectable state; and wherein an input address has a predetermined number of bits set to the first selectable state. - View Dependent Claims (15, 16, 17, 18, 28)
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19. A method for optimizing the operation of a computer memory which comprises a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states, a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines, means to receive an input address, and means to activate one or more of the address decoders if a comparison between a decoder identifier and the input address exceeds a predetermined comparison threshold;
- said method comprising;
determining an operationally beneficial number of address decoders to be activated in response to a valid input address, and configuring the comparison threshold such that a valid input address will activate a number of address decoders equal to the operationally beneficial number of address decoders to be activated. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
- said method comprising;
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29. A memory configuration for use in a computer system, the memory comprising:
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a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select a predetermined one of the plurality of word lines; the address decoders comprising means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address, and wherein the memory further comprises means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.
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30. A method for operating a memory for use in a computer system, the method comprising:
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allocating to each of a plurality of address decoders an identifier having a predetermined number of bits, each bit having first and second selectable states; and activating each of said address decoders to select a predetermined one of a plurality of word lines in a data memory having a plurality of word lines of predetermined length, wherein an input address having a predetermined number of bits is input to the address decoder, the identifier of an address decoder is compared with the input address and address decoders are activated if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.
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31. A memory configuration for use in a computer system, the memory comprising:
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a plurality of address decoders, each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states; and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines; the address decoders including means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address; wherein the memory further includes means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier; wherein the data memory comprises a plurality of single bit memories, such that each bit of each word line is stored in a single bit memory; and wherein the data memory comprises a data input line containing an equal number of bits to each of the plurality of word lines, the data input line being configured to receive input data containing a predetermined number of bits set to the first selectable state.
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Specification