Multi-voltage synchronous systems

• US 7,512,842 B2
• Filed: 03/17/2006
• Issued: 03/31/2009
• Est. Priority Date: 08/29/2005
• Status: Expired due to Fees

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Mangione-Smith, William Henry
• Primary Examiner(s): Baderman; Scott T.
• Assistant Examiner(s): Leibovich; Yair
• Application Number:
  US11/384,237
• Publication Number:
  US 20070050582A1
• Time in Patent Office: 1,110 Days
• Field of Search: 714/14
• US Class Current: 714/55
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/0706 the processing taking place on a specific hardware platform or in a specific software environment
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1405 at machine instruction level
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: G06F 11/3471 Address tracing
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Claims

1. A system comprising:

a synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage;

an error detector operable to detect a computational error corresponding to a setup/hold violation; and

a controller operable to change the first power plane voltage based upon the detected incidence of a computational error.