Dual work function metal gate structure and related method of manufacture

• US 7,514,310 B2
• Filed: 07/29/2005
• Issued: 04/07/2009
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-Ho, Jung, Hyung-Suk, Kim, Min-Joo, Han, Sungkee
• Primary Examiner(s): Sarkar; Asok K
• Application Number:
  US11/192,288
• Publication Number:
  US 20060115940A1
• Time in Patent Office: 1,348 Days
• Field of Search: 257/E21.623, 257/407, 438/199
• US Class Current: 438/199
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine.

Claims

1. A method, comprising:

forming a metal layer having a first work function;

adjusting the work function of a selected portion of the metal layer by doping the selected portion with fluorine (F), such that the work function of the selected portion of the metal layer is reduced to a second work function less than the first work function as a function of the doping with fluorine.

2. The method of claim 1, wherein doping the selected portion of the metal layer with fluorine comprising selectively implanting fluorine atoms.

3. The method of claim 1, wherein the first work function ranges from between about 4.7 to 5.3 eV, and wherein the second work function ranges from between about 3.7 to 4.5 eV.

4. The method of claim 3, wherein the first work function ranges from between about 4.7 to 5.0 eV, and wherein the second work function ranges from between about 4.3 to 4.5 eV.

5. The method of claim 1, wherein the metal layer comprises at least one of nickel (Ni), ruthenium oxide (RuO), molybdenum nitride (MoN), molybdenum silicide (MoSi₂), tantalum silicide (TaSi₂), and tantalum nitride (TaN).

6. The method of claim 1, wherein forming the metal layer comprises depositing the metal layer on the substrate using a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

7. The method of claim 6, wherein the metal layer comprises tantalum nitride, and wherein forming the metal layer comprises depositing the tantalum nitride on the substrate using a CVD process.

8. The method of claim 6, further comprising:

applying a heat treatment to the metal layer.

9. The method of claim 8, wherein the heat treatment is applied to the metal layer at least once before doping with fluorine and after doping with fluorine.

10. A method, comprising:

forming a metal layer having a first work function;

adjusting the first work function in a selected portion of the metal layer by doping the selected portion with carbon (C), such that the selected portion of the metal layer has a second work function greater than the first work function.

11. The method of claim 10, wherein the first work function ranges from between about 3.7 to 4.5 eV and wherein the second work function ranges from between about 4.7 to 5.3 eV.

12. The method of claim 10, wherein the first work function ranges from between about 4.3 to 4.5 eV and wherein the second work function ranges from between about 4.7 to 5.0 eV.

13. The method of claim 10, wherein the metal layer comprises at least one of ruthenium (Ru), zirconium (Zr), niobium (Nb) and tantalum (Ta).

14. The method of claim 10, further comprising:

applying a heat treatment to the metal layer at least once before doping with carbon or after doping with carbon.

15. A method, comprising:

forming an NMOS active region and a PMOS active region in a substrate;

forming a gate insulating layer on the substrate covering the NMOS active region and the PMOS active region;

forming a metal layer having a first work function on the gate insulating layer;

adjusting the first work function in a selected portion of the metal layer by doping the selected portion with either fluorine to decrease the first work function or carbon to increase the first work function, such that the selected portion has a second work function different from the first work function.

16. The method of claim 15, wherein the first work function is PMOS-compatible and the selected portion is doped with fluorine to make the second work function NMOS-compatible.

17. The method of claim 16, wherein the metal layer comprises at least one of nickel (Ni), ruthenium oxide (RuO), molybdenum nitride (MoN), molybdenum silicide (MoSi₂), tantalum silicide (TaSi₂), and tantalum nitride (TaN).

18. The method of claim 15, wherein the first work function is NMOS-compatible and the selected portion is doped with carbon to the make the second work function PMOS-compatible.

19. The method of claim 18, wherein the metal layer comprises at least one of ruthenium (Ru), zirconium (Zr), niobium (Nb) and tantalum (Ta).

20. The method of claim 15, further comprising:

forming a buffer layer on the metal layer.

21. The method of claim 20, wherein the buffer layer comprises at least one of poly-silicon and silicon dioxide (SiO₂).

22. The method of claim 15, wherein adjusting the work function in the selected portion further comprises:

forming a mask pattern on a portion of the metal layer other than the selected portion; and

ion implanting either fluorine atoms or carbon atoms in the selected portion.

23. The method of claim 22, further comprising:

forming an additional conductive layer on the metal layer.

24. The method of claim 23, wherein the additional conductive layer comprises at least one of poly-silicon, a refractory metal, and a refractory metal silicide.

25. The method of claim 23, further comprising:

forming a PMOS metal gate structure on the PMOS active region and a NMOS metal gate structure on the NMOS active region by selectively patterning the gate insulating layer, the metal layer including the selected portion, and the additional conductive layer.

26. The method of claim 25, wherein the PMOS metal gate structure and NMOS metal gate structure comprise sidewalls, and wherein the method further comprises:

forming respective source and drain regions in the NMOS and PMOS active regions in relation to the PMOS and NMOS metal gate structures using the respective sidewalls as an implant mask.

27. A method, comprising:

forming an NMOS active region and a PMOS active region in a substrate;

forming a gate insulating layer on the substrate covering the NMOS active region and the PMOS active region;

forming a metal layer having a mid-bandgap work function on the gate insulating layer;

adjusting the work function in a first selected portion of the metal layer formed on the NMOS active region by doping the first selected portion with fluorine, such that the first selected portion has a NMOS-compatible work function; and

,

adjusting the work function in a second selected portion of the metal layer formed on the PMOS active region by doping the second selected portion with carbon, such that the second selected portion has a PMOS-compatible work function.

28. The method of claim 27, wherein the metal layer comprises at least one of tungsten nitride (WN) and titanium nitride (TiN).

29. The method of claim 27, further comprising:

forming a buffer layer on the metal layer.

30. The method of claim 29, wherein the buffer layer comprises at least one of poly-silicon and silicon dioxide (SiO₂).

31. The method of claim 27, wherein adjusting the work function in the first selected portion of the metal layer further comprises:

forming a first mask pattern on the second selected portion of the metal layer and ion implanting fluorine atoms in the first selected portion of the metal layer.

32. The method of claim 31, wherein adjusting the work function in the second selected portion of the metal layer further comprises:

forming a second mask pattern on the first selected portion of the metal layer and ion implanting carbon atoms in the second selected portion of the metal layer.

33. The method of claim 27, further comprising:

forming an additional conductive layer on the metal layer.

34. The method of claim 33, wherein the additional conductive layer comprises at least one of poly-silicon, a refractory metal, and a refractory metal silicide.

35. The method of claim 33, further comprising:

forming a PMOS metal gate structure on the PMOS active region and a NMOS metal gate structure on the NMOS active region by selectively patterning the gate insulating layer, the metal layer including the first and second selected portions of the metal layer, and the additional conductive layer;

wherein the NMOS metal gate structure is formed in part from the first selected portion of the metal layer and the PMOS metal gate structure is formed in part from the second portion of the metal layer other than the selected portion of the metal layer.

36. The method of claim 35, wherein the PMOS metal gate structure and NMOS metal gate structure comprise sidewalls, and wherein the method further comprises:

forming respective source and drain regions in the NMOS and PMOS active regions in relation to the PMOS and NMOS metal gate structures using the respective sidewalls as an implant mask.

37. A method of forming a semiconductor device having a NMOS metal gate structure and a PMOS metal gate structure, the method comprising:

forming a single metal layer having an initial work function on a gate insulating layer;

adjusting the work function for a selected portion of the metal layer by doping either a first selected portion with fluorine to decrease the initial work function, or a second selected portion with carbon to increase the initial work function;

wherein either the PMOS metal gate structure is formed from a first metal gate electrode formed from the second selected portion of the metal layer, or the NMOS metal gate structure is formed from a second metal gate electrode formed from the second selected portion of the metal layer.

38. A method of defining a dual work functions in respective portions of a metal layer, comprising:

selecting a metal type, a formation process adapted to the metal type, and related process conditions to form the metal layer having an initial work function;

selectively doping a first portion of the metal layer with carbon to increase the initial work function, and selectively doping a second portion of the metal layer with fluorine to decrease the initial work function.

39. The method of claim 38, wherein the formation process comprises a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

40. The method of claim 39, wherein one of the related process conditions comprises application of a heat treatment.