Shielded gate field effect transistor
First Claim
1. A method of forming a FET comprising:
- providing a semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region;
performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer;
forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion;
performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, the lower trench portion being narrower than the upper trench portion; and
performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.
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Accused Products
Abstract
A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.
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Citations
18 Claims
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1. A method of forming a FET comprising:
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providing a semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region; performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer; forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion; performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, the lower trench portion being narrower than the upper trench portion; and performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a MOSFET comprising:
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providing a substrate of a first conductivity type with an epitaxial layer of a second conductivity extending over the substrate; performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer; forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion; performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the substrate, the lower trench portion being narrower than the upper trench portion; performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion; forming a shield dielectric lining sidewalls and bottom surface of the lower trench portion; forming a shield electrode in the lower trench portion; forming a gate dielectric layer along sidewalls of the upper trench portion; and forming a gate electrode in the upper trench portion over but insulated from the shield electrode. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A MOSFET comprising:
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a trench having a lower portion and an upper portion, the lower portion being narrower than the upper portion, the trench extending into a semiconductor region; a shield electrode in the lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric; a gate electrode in the upper portion of the trench, the gate electrode being over but insulated from the shield electrode; wherein the semiconductor region comprises; a substrate of a first conductivity type; a first silicon region of a second conductivity type over the substrate, the first silicon region having a first portion extending to a depth intermediate a top surface and a bottom surface of the gate electrode, the first silicon region having a second portion extending to a depth intermediate a top surface and a bottom surface of the shield electrode; a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region, the second silicon region having a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion; and a source region of the first conductivity type in the first silicon region, the source region being adjacent the upper trench portion. - View Dependent Claims (16, 17, 18)
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Specification