Semiconductor device

• US 7,514,748 B2
• Filed: 09/15/2005
• Issued: 04/07/2009
• Est. Priority Date: 04/18/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Fazan, Pierre, Okhonin, Serguei
• Primary Examiner(s): Wilczewski, M.
• Assistant Examiner(s): Thomas, Toniae M
• Application Number:
  US11/226,978
• Publication Number:
  US 20060006468A1
• Time in Patent Office: 1,300 Days
• Field of Search: 257347-348, 257/392, 257/E29.276, 257/68, 257/69, 257/E27.084, 257/E27.112
• US Class Current: 257/348
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).

Claims

1. An integrated circuit device, disposed on or in a first semiconductor region or layer which resides on or above an insulating region or layer, wherein the insulating region or layer is disposed on or over a substrate, the integrated circuit device comprising:

a first portion including a plurality of transistors, wherein each transistor includes;

a source region disposed on or in the first semiconductor region;

a drain region disposed on or in the first semiconductor region;

a body region disposed on or in the first semiconductor region and between the source region, the drain region, and the insulating region or layer, wherein the body region is electrically floating;

a gate disposed over the body region; and

a second portion including a plurality of transistors, wherein each transistor includes;

a source region disposed in or on the first semiconductor region;

a drain region disposed in or on the first semiconductor region;

a body region disposed in or on the first semiconductor region and between the source region, the drain region, and the insulating region or layer;

a gate disposed over the body region; and

wherein the integrated circuit device further includes a second semiconductor region or layer disposed on or in the substrate and juxtaposed the body region of each transistor of the first portion of the integrated circuit device and separated therefrom by the insulating region or layer, and wherein the second semiconductor region or layer is not disposed on or in a portion of the substrate juxtaposed the body region of each transistor of the second portion of the integrated circuit device.

2. The integrated circuit device of claim 1 wherein the body region of each transistor of the second portion of the integrated circuit device is fully-depleted.

3. The integrated circuit device of claim 2 wherein the body region of each transistor of the first portion of the integrated circuit device is partially-depleted.

4. The integrated circuit device of claim 2 wherein the second semiconductor region or layer is connected to a voltage that provides a neutral zone in the body region of each transistor of the first portion of the integrated circuit device.

5. The integrated circuit device of claim 4 wherein the voltage is a constant voltage.

6. The integrated circuit device of claim 1 wherein the second semiconductor region or layer is connected to a voltage that provides a neutral zone in the body region of each transistor of the first portion of the integrated circuit device such that an electric charge may be generated in, stored in and/or eliminated from the neutral zone in the body region of each transistor of the first portion of the integrated circuit device.

7. The integrated circuit device of claim 6 wherein the body region of each transistor of the second portion of the integrated circuit device is fully-depleted.

8. The integrated circuit device of claim 6 wherein the voltage is a constant or fixed voltage.

9. The integrated circuit device of claim 6 further including a contact area to connect a conductive line to the second semiconductor region or layer.

10. The integrated circuit device of claim 9 wherein the contact area connects the conductive line to the second semiconductor region or layer from above the substrate.

11. The integrated circuit device of claim 1 wherein the integrated circuit device is a DRAM memory device.

12. The integrated circuit device of claim 1 wherein an electric charge is capable of being stored in the body region of each transistor of the first portion of the integrated circuit device in response to a voltage applied to the second semiconductor region or layer and wherein each transistor of the first portion of the integrated circuit device includes:

a first data state representative of a first charge in the body region; and

a second data state representative of a second charge in the body region.

13. The integrated circuit device of claim 12 wherein the body region of each transistor of the second portion of the integrated circuit device is fully-depleted.

14. An integrated circuit device, disposed on or in a first semiconductor region or layer which resides on or above an insulating region or layer, wherein the insulating region or layer is disposed on or over a substrate, the integrated circuit device comprising:

a memory portion having a plurality of partially-depleted transistors, each partially-depleted transistor includes;

a source region disposed on or in the first semiconductor region;

a drain region disposed on or in the first semiconductor region;

a body region disposed on or in the first semiconductor region and between the source region, the drain region, and the insulating region or layer, wherein the body region is electrically floating; and

a gate disposed over the body region; and

a second portion having a plurality of fully-depleted transistors, each fully-depleted transistor includes;

a source region disposed in or on the first semiconductor region;

a drain region disposed in or on the first semiconductor region;

a body region disposed in or on the first semiconductor region and between the source region, the drain region, and the insulating region or layer;

a gate disposed over the body region.

15. The integrated circuit device of claim 14 wherein the integrated circuit device further includes a second semiconductor region or layer disposed on or in the substrate and juxtaposed the body region of each partially-depleted transistor of the memory portion of the integrated circuit device and separated therefrom by the insulating region or layer, and wherein the second semiconductor region or layer is not disposed on or in a portion of the substrate juxtaposed the body region of each fully-depleted transistor of the second portion of the integrated circuit device.

16. The integrated circuit device of claim 15 wherein the second semiconductor region or layer is connected to a voltage that provides a neutral zone in the body region of each partially-depleted transistor of the memory portion of the integrated circuit device.

17. The integrated circuit device of claim 16 wherein the voltage is a constant or fixed voltage.

18. The integrated circuit device of claim 15 further including a contact area to connect a conductive line to the second semiconductor region or layer.

19. The integrated circuit device of claim 18 wherein the contact area connects the conductive line to the second semiconductor region or layer from above the substrate.

20. The integrated circuit device of claim 15 wherein an electric charge is capable of being stored in the body region of each partially-depleted transistor of memory portion of the integrated circuit device in response to a voltage applied to the second semiconductor region or layer and wherein each partially-depleted transistor of the memory portion of the integrated circuit device includes:

a first data state representative of a first charge in the body region; and

a second data state representative of a second charge in the body region.

21. The integrated circuit device of claim 14 wherein the integrated circuit device is a DRAM memory device.

22. The integrated circuit device of claim 15 wherein an electric charge is capable of being stored in the body region of each partially-depleted transistor of the memory portion of the integrated circuit device in response to a voltage applied to the second semiconductor region or layer.

23. The integrated circuit device of claim 22 further including a contact area to connect a conductive line to the second semiconductor region or layer, wherein the contact area connects the conductive line to the second semiconductor region or layer from above the substrate.

24. The integrated circuit device of claim 23 wherein the voltage is a constant or fixed voltage.

25. The integrated circuit device of claim 14 wherein an electric charge is capable of being stored in the body region of each partially-depleted transistor of the memory portion of the integrated circuit device and wherein each partially-depleted transistor comprises a memory cell which includes:

a first data state representative of a first charge in the body region; and

a second data state representative of a second charge in the body region.

26. The integrated circuit device of claim 25 wherein the integrated circuit device is a DRAM memory device.