Piezoelectric MEMS integration with GaN technology

• US 7,514,759 B1
• Filed: 04/11/2005
• Issued: 04/07/2009
• Est. Priority Date: 04/19/2004
• Status: Expired due to Fees

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Grider, David E., Mehta, Sarabjit, Wong, Wah S.
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US11/104,395
• Time in Patent Office: 1,457 Days
• Field of Search: 438/191, 438/55, 333/187, 310/332, 257/194, 257/416
• US Class Current: 257/416
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H03H 2003/021 the resonators or networks being of the air-gap type
• CPC Class Codes: H03H 3/02 for the manufacture of piezoelectric or electrostrictive resonators or networks H03H3/08 takes precedence
• CPC Class Codes: H03H 9/0542 consisting of a lateral arrangement H03H9/0566 takes precedence

Abstract

A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.

Claims

1. A process for fabricating a combined micro electromechanical/gallium nitride (GaN) structure, the process comprising:

providing a substrate;

depositing a GaN layer on the substrate;

obtaining a GaN transistor structure;

depositing and patterning a first metal layer on the GaN layer;

depositing a non-metal separation layer on the GaN layer and on the GaN transistor structure;

patterning the non-metal separation layer to form a protective region to protect the GaN transistor structure;

depositing a sacrificial layer on the protective region, the patterned first metal layer and at least a portion of the GaN layer so as to leave a further portion of the GaN layer between the protective region and the patterned first metal layer exposed;

depositing and patterning a second metal layer on the sacrificial layer;

depositing a support layer on the sacrificial layer, the patterned second metal layer and the exposed GaN layer;

providing a piezoelectric structure on the support layer;

patterning the support layer in proximity of the GaN transistor structure to provide access holes;

removing the non-metal separation layer and the sacrificial layer from the proximity of the GaN transistor structure through the access holes;

providing a metal overlay above the GaN transistor structure, the metal overlay forming a gate of the GaN transistor structure;

providing a gate passivation layer above the gate of the GaN transistor structure;

providing a further metal layer above the gate passivation layer; and

removing the sacrificial layer between the first patterned metal layer and the second patterned metal layer.

2. The process of claim 1, wherein the GaN transistor structure is a GaN FET structure.

3. The process of claim 1, wherein the step of obtaining a GaN transistor structure comprises a step of providing ohmic contacts and a device isolation step.

4. The process of claim 1, wherein the GaN transistor structure is protected during the step of depositing and patterning the first metal layer on the GaN layer.

5. The process of claim 1, wherein the patterned first contact layer and second contact layer form respective first and second contact pads.

6. The process of claim 5, wherein the second contact pad is located above the first contact pad.

7. The process of claim 1, wherein the support layer has an adjustable thickness to compensate for any stress related bending.

8. The process of claim 1, wherein piezoelectric regions of the piezoelectric structure are protected during the step of removing the non-metal separation layer and the sacrificial layer from the GaN transistor structure through the access holes.

9. The process of claim 1, wherein the piezoelectric structure is protected during the step of providing a metal overlay above the GaN transistor structure.

10. The process of claim 1, wherein the metal overlay is used to provide a metal portion of the piezoelectric structure.

11. The process of claim 10, wherein the metal portion of the piezoelectric structure is an electrode of the piezoelectric structure.

12. The process of claim 1, wherein the piezoelectric structure is protected during the step of providing a gate passivation layer above the gate.

13. The process of claim 1, wherein the piezoelectric structure is a MEMS piezoelectric switch.

14. An integrated gallium nitride (GaN) field emitter transistor (FET)/micro electromechanical switch device fabricated with a process according to claim 1.

15. An integrated gallium nitride (GaN) field emitter transistor (FET) disposed on a first surface of a gallium nitride (GaN) substrate and a piezoelectric micro electromechanical switch device also disposed on said first surface of said gallium nitride (GaN) substrate.

16. A process for fabricating a combined micro electromechanical/gallium nitride (GaN) structure, the process comprising:

depositing a GaN layer;

obtaining a GaN transistor structure on the GaN layer;

forming a first metal contact pad on the GaN layer;

forming a protective region around the GaN transistor structure;

depositing a sacrificial layer on the protective region and the first metal contact pad;

forming a second metal contact pad on the sacrificial layer;

depositing a support layer on the sacrificial layer and the second metal contact pad;

providing a piezoelectric structure on the support layer;

removing the sacrificial layer from the proximity of the GaN transistor structure;

patterning the piezoelectric structure in correspondence of the first metal contact pad and the second metal contact pad;

forming a gate of the GaN transistor structure;

providing a gate passivation layer above the gate of the GaN transistor structure;

providing a further metal layer above the gate passivation layer; and

removing the sacrificial layer between the first metal contact pad and the second metal contact pad.

17. The process of claim 16, wherein the piezoelectric structure is a piezoelectric switch.

18. The process of claim 17, wherein the piezoelectric switch comprises electrode layers alternated with piezoelectric layers.

19. A process for fabricating a combined gallium nitride (GaN)/piezoelectric structure comprising:

obtaining a GaN structure on a GaN layer;

forming a first metal contact pad on the GaN layer separated from the GaN structure;

forming a protective region around the GaN structure;

depositing a sacrificial layer on the protective region and the first metal contact pad;

forming a second metal contact pad on the sacrificial layer;

depositing a support layer on the sacrificial layer and the second metal contact pad;

providing a piezoelectric switch structure on the support layer;

removing the sacrificial layer from the proximity of the GaN structure; and

patterning the piezoelectric switch structure in correspondence of the first metal contact pad and the second metal contact pad.

20. A process for fabricating a combined gallium nitride (GaN)/piezoelectric structure comprising:

obtaining a GaN structure on a GaN layer;

forming a first metal contact pad on the GaN layer separated from the GaN structure;

forming a protective region around the GaN structure;

depositing a sacrificial layer on the protective region and the first metal contact pad;

forming a second metal contact pad on the sacrificial layer;

depositing a support layer on the sacrificial layer and the second metal contact pad;

providing a piezoelectric bulk acoustic wave resonator structure on the support layer;

removing the sacrificial layer from the proximity of the GaN structure; and

patterning the piezoelectric switch structure in correspondence of the first metal contact pad and the second metal contact pad.

21. An integrated gallium nitride (GaN) field emitter transistor (FET)/micro electromechanical switch device fabricated according to the process of claim 20.

22. A process for fabricating a combined micro electromechanical/gallium nitride (GaN) structure, the process comprising:

providing a substrate;

depositing a GaN layer on the substrate;

obtaining a GaN transistor structure;

depositing a non-metal separation layer on the GaN layer in correspondence of the GaN transistor structure;

patterning the non-metal separation layer to form a protective region around the GaN transistor structure;

depositing a sacrificial layer on at least a portion of the GaN layer and on the protective region;

creating at least a cavity in the sacrificial layer;

depositing a support layer on the sacrificial layer and the cavity;

providing a piezoelectric structure on the support layer;

patterning the support layer in proximity of the GaN transistor structure to provide access holes;

removing the non-metal separation layer and the sacrificial layer from the proximity of the GaN transistor structure through the access holes;

patterning the piezoelectric structure in correspondence of a patterned first metal layer and patterned second metal layer;

providing a metal overlay above the GaN transistor structure, the metal overlay forming a gate of the GaN transistor structure;

providing a gate passivation layer above the gate of the GaN transistor structure;

providing a further metal layer above the gate passivation layer; and

removing the sacrificial layer between the GaN layer and the support layer.

23. The process of claim 22, wherein the GaN transistor structure is a GaN FET structure.

24. The process of claim 22, wherein the support layer has an adjustable thickness to compensate for any stress related bending.

25. The process of claim 22, wherein piezoelectric regions of the piezoelectric structure are protected during the step of removing the non-metal separation layer and the sacrificial layer from the GaN transistor structure through the access holes.

26. The process of claim 22, wherein the piezoelectric structure is protected during the step of providing a metal overlay above the GaN transistor structure.

27. The process of claim 22, wherein the piezoelectric structure is protected during the step of providing a gate passivation layer above the gate.

28. The process of claim 22, wherein the piezoelectric structure is a bulk acoustic wave (BAW) device.

29. An integrated gallium nitride (GaN) field emitter transistor (FET)/bulk acoustic wave (BAW) device fabricated with a process according to claim 22.

30. An integrated gallium nitride (GaN) field emitter transistor (FET) disposed on a first surface of a gallium nitride (GaN) substrate and a bulk acoustic wave (BAW) device also disposed on said first surface of said gallium nitride (GaN) substrate.

31. A process for fabricating a combined micro electromechanical/gallium nitride (GaN) structure, the process comprising:

depositing a GaN layer;

obtaining a GaN transistor structure on the GaN layer;

forming a first contact pad on the GaN layer;

forming a protective region around the GaN transistor structure;

depositing a sacrificial layer on the protective region and the first contact pad;

forming a second contact pad on the sacrificial layer;

depositing a support layer on the sacrificial layer and the second contact pad;

providing a piezoelectric structure on the support layer;

removing the sacrificial layer from the proximity of the GaN transistor structure;

patterning the piezoelectric structure in correspondence of the first contact pad and the second contact pad; and

removing the sacrificial layer between the first contact pad and the second contact pad.

32. The process of claim 31, wherein the piezoelectric structure is a piezoelectric switch.