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Voltage comparator circuit with symmetric circuit topology

  • US 7,514,965 B2
  • Filed: 11/16/2005
  • Issued: 04/07/2009
  • Est. Priority Date: 11/17/2004
  • Status: Expired due to Fees
First Claim
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1. A voltage comparator circuit comprising:

  • a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal; and

    a waveform shaping circuit achieving waveform shaping of said output signal received from said differential amplifier circuit,wherein said differential amplifier circuit includes;

    a first differential transistor pair responsive to said pair of input signals to output first and second output currents;

    a second differential transistor pair complementary to said first differential transistor pair, and responsive to said pair of input signals to output third and fourth output currents;

    a first current mirror circuit developing a first internal current in response to said first output current;

    a third current mirror circuit complementary to said first current mirror circuit and developing a third internal current in response to said third output current;

    a second current mirror circuit developing a second internal current in response to said second output current and said third internal current; and

    a fourth current mirror circuit complementary to said second current mirror circuit and developing a fourth internal current in response to said fourth output current and said first internal current,wherein a resultant current which is said second and fourth internal currents added together is drawn from or supplied to said output terminal of said differential amplifier circuit,wherein said first differential transistor pair comprises first and second MOS transistors of a first conductive type,wherein said second differential transistor pair comprises third and fourth MOS transistors of a second conductive type complementary to said first conductive type,wherein said differential amplifier circuit further includes;

    a first constant current source connected to commonly-connected sources of said first and second MOS transistors; and

    a second constant current source connected to commonly-connected sources of said third and fourth MOS transistors,wherein a drain of said first MOS transistor is connected to an input of said first current mirror circuit,wherein a drain of said second MOS transistor is connected to an input of said second current mirror circuit,wherein a drain of said third MOS transistor is connected to an input of said third current mirror circuit,wherein a drain of said fourth MOS transistor is connected to an input of said fourth current mirror circuit,wherein gates of said first and third MOS transistors are commonly connected to one of input terminals of said differential amplifier circuit,wherein gates of said second and fourth MOS transistors are commonly connected to another of said input terminals of said differential amplifier circuit,wherein each of said first to fourth current mirror circuits includes;

    fifth and sixth MOS transistors having commonly-connected gates and commonly-connected sources;

    a seventh MOS transistor having a drain connected to said commonly-connected gates of said fifth and sixth MOS transistors, and a source connected to a drain of said fifth MOS transistor, a gate of said seventh MOS transistor being connected to a constant voltage source;

    a constant current source connected to said drain of said seventh MOS transistor;

    a current input connected to said drain of said fifth MOS transistor and to said source of said seventh MOS transistor;

    a common terminal connected to said commonly-connected sources of said fifth and sixth MOS transistors; and

    a current output connected directly to a drain of said sixth MOS transistor.

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