Method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog-to-digital converter (ADC)

• US 7,515,076 B1
• Filed: 09/28/2007
• Issued: 04/07/2009
• Est. Priority Date: 09/28/2007
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Fang, Jie, Sood, Mohit, Singh, Rahul, De Angel, Edwin, Drakshapalli, Prashanth
• Primary Examiner(s): Nguyen; Khai M
• Application Number:
  US11/864,876
• Time in Patent Office: 557 Days
• Field of Search: 341/122, 341/123, 341/155
• US Class Current: 341/122
• CPC Class Codes: H03M 3/376 Prevention or reduction of switching transients, e.g. glitches
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step

Abstract

A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.

Claims

1. An integrated circuit, comprising:

an analog-to-digital converter for receiving an analog input signal and providing a digital output, wherein a discrete-time sampling circuit of the analog-to-digital converter is responsive to a first clock signal to sample the analog input signal;

a digital logic circuit for performing processing operations within the integrated circuit, wherein the digital logic circuit is responsive to a second clock signal to cause transitions of logic within the digital logic circuit; and

a clock generator circuit for receiving a master clock signal and providing the first clock signal and the second clock signal as frequency divisions of the master clock signal, wherein the clock generator circuit includes a first clock divider for generating the first clock signal from the master clock signal and a second clock divider for generating the second clock signal from the master clock signal, and wherein the clock generator circuit adjusts an edge relationship between the first clock signal and the second clock signal such that transitions of the second clock signal do not occur near critical sampling edges of the first clock signal by presetting the first clock divider or the second clock divider with an offset value, whereby sampling error in the analog-to-digital converter due to transition noise coupled from the digital logic circuit is substantially eliminated.

2. The integrated circuit of claim 1, wherein the digital logic circuit comprises a processor core, and wherein the processor core is coupled to a memory having program instructions for execution by the processor core, wherein the program instructions include program instructions for presetting the first clock divider or the second clock divider with an offset value.

3. The integrated circuit of claim 2, wherein the program instructions for presetting preset the second clock divider, and wherein the clock generator circuit generates a synchronization signal in conformity with an output of the first clock divider, and wherein the program instructions for presetting are executed in response to the synchronization signal.

4. The integrated circuit of claim 3, wherein the program instructions for presetting are further executed in response to initialization of the analog-to-digital converter, whereby subsequent assertions of the synchronization signal do not trigger the presetting.

5. The integrated circuit of claim 1, wherein the clock generator is further responsive to a halting signal, wherein the clock generator stops generating the second clock signal in response to the halting signal and presets the second clock divider while the second clock signal is not being generated.

6. The integrated circuit of claim 5, wherein the halting signal is a power down signal for stopping operation of the digital logic circuit.

7. The integrated circuit of claim 5, wherein the digital logic circuit comprises a processor core, and wherein the processor core is coupled to a memory having program instructions for execution by the processor core, wherein the program instructions include program instructions for presetting the second clock divider with an offset value, wherein the clock generator stores the offset value in a latch, halts the second clock divider in response to a halting signal, thereby stopping execution within the processor core, and loads the offset value into the second clock divider in response to a synchronization signal generated in conformity with an output of the first clock divider, and wherein the second clock divider is subsequently restarted at the offset value.

8. The integrated circuit of claim 1, wherein the clock generator comprises control logic for receiving an offset value, wherein the clock generator stores the offset value in a latch, halts the second clock divider in response to a halting signal, thereby stopping operation of the digital logic circuit, and loads the offset value into the second clock divider in response to a synchronization signal generated in conformity with an output of the first clock divider, and wherein the second clock divider is subsequently restarted at the offset value.

9. The integrated circuit of claim 1, wherein the presetting is performed in response to initialization of the analog-to-digital converter.

10. The integrated circuit of claim 1, further comprising a power converter operated by a clock having edges aligned with the second clock signal, whereby sampling error in the analog-to-digital converter due to power converter noise coupled from the power converter is substantially eliminated.

11. The integrated circuit of claim 1, further comprising a power converter operated by a switching clock signal, wherein the clock generator prevents switching of the power converter in a predetermined window around the critical sampling edges, whereby sampling error in the analog-to-digital converter due to power converter noise coupled from the power converter is substantially eliminated.

12. A method of reducing noise in an integrated circuit having a discrete time sampling analog-to-digital converter and digital logic circuit, comprising:

generating a first clock signal and a second clock signal from a master clock signal;

clocking a discrete time sampling circuit of the analog-to-digital converter with the first clock signal;

clocking the digital logic circuit with the second clock signal; and

adjusting an edge relationship between the second clock signal and the first clock signal by setting an offset of a divider that generates the second clock signal, such that transitions of the second clock signal do not occur near critical sampling edges of the first clock signal, whereby sampling error in the analog-to-digital converter due to transition noise coupled from the digital logic circuit is substantially eliminated.

13. The method of claim 12, wherein the digital logic circuit comprises a processor executing program instructions that perform the adjusting by setting the offset in response to a synchronization signal derived from the first clock signal.

14. The method of claim 12, further comprising halting the generation of the second clock signal during the adjusting.

15. The method of claim 12, wherein the adjusting further adjusts edges of switching signals of a power converter, whereby sampling error in the analog-to-digital converter due to power converter noise coupled from the power converter is substantially eliminated.

16. An analog-to-digital converter integrated circuit including a digital processing circuit, an analog sampling circuit, and a clock generator for generating digital clock signals for the digital processing circuit and sampling clock signals to the analog sampling circuit, wherein the clock generator circuit adjusts a delay of the digital clock signals by programming an offset of a divider within the clock generator that generates the digital clock signals such that edges of the digital clock signal are away from critical sampling edges of the sampling clock signals.

17. The analog-to-digital converter integrated circuit of claim 16, further comprising a memory for storing program instructions for execution by the digital processing circuit, and wherein the program instructions include program instructions for setting an offset value within the clock generator, and initiating an operation by the clock generator that halts the digital clock signals, loads the offset value into a clock generator divider circuit and restarts the digital clock signals.

18. The analog-to-digital converter integrated circuit of claim 16, further comprising a power converter operated by a switching clock signal, wherein the clock generator further prevents switching of the power converter in a predetermined window around the critical sampling edges, whereby sampling error in the analog-to-digital converter due to power converter noise coupled from the power converter is substantially eliminated.