Pixel sensor

• US 7,515,186 B2
• Filed: 02/17/2004
• Issued: 04/07/2009
• Est. Priority Date: 02/17/2003
• Status: Expired due to Fees

• Current Assignee: Silverbrook Research Pty Limited
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia, Moini, Alireza, Yourlo, Zhenya Alexander, Lapstun, Paul, Underwood, Matthew John, Ridley, Nicholas Damon, Henderson, Peter Charles Boyd
• Primary Examiner(s): Ometz; David L
• Assistant Examiner(s): PRABHAKHER, PRITHAM DAVID
• Application Number:
  US10/778,059
• Publication Number:
  US 20050024512A1
• Time in Patent Office: 1,876 Days
• Field of Search: 348294-310
• US Class Current: 348/294
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A photodetecting circuit comprising a photodetector for generating a signal in response to incident light; a storage node having first and second node terminals, the first node terminal being connected to the photodetector to receive the signal such that charge stored in the node changes during an integration period of the photodetecting circuit; and

an output circuit for generating an output signal during a read period of the photodetecting circuit, the output signal being at least partially based on a voltage at the first terminal; the photodetecting circuit being configured to receive a reset signal; integrate charge in the storage node during an integration period following receipt of the reset signal; and receive a compensation signal at the second terminal of the storage node at least during the read period, the compensation signal increasing the voltage at the first terminal whilst the output circuit generates the output signal.

Claims

1. A photodetecting circuit comprising:

a photodetector for generating a signal in response to incident light;

a storage node having first and second node terminals;

a transfer transistor disposed intermediate the first node terminal and the photodetector, a control node of the transfer transistor receiving a transfer signal, such that when the transfer signal is asserted during an integration period of the photodetecting circuit, the first node terminal and the photodetector are electrically connected such that charge stored in the storage node changes the storage node during the integration period;

a reset transistor having a control node for receiving a reset signal, a first terminal for receiving a reset voltage, and a second terminal electrically connected to the first node terminal, such that the reset voltage is supplied to the first node terminal when the reset signal is asserted at the control node; and

an output circuit for generating an output signal during a read period of the photodetecting circuit, the output signal being at least partially based on a voltage at the first terminal;

the photodetecting circuit being configured to;

receive the reset signal;

integrate charge in the storage node during the integration period following receipt of the reset signal; and

receive a compensation signal at the second terminal of the storage node at least during the read period, the compensation signal increasing the voltage at the first terminal whilst the output circuit generates the output signal, wherein the compensation signal is a logically negated version of the transfer signal.

2. A photodetecting circuit according to claim 1, wherein the storage node includes a capacitor.

3. A photodetector circuit according to claim 1, the photodetector circuit being a CMOS circuit.

4. A monolithic integrated circuit including:

a plurality of photodetector circuits according to claim 1;

at least one analog to digital converter for converting output signals generated by respective photodetector circuits into digital image data; and

a framestore for storing frames of the digital image data.

5. A monolithic integrated circuit including:

an image sensor for capturing image information, the image sensor incorporating a plurality of photodetector circuits according to claim 1;

at least one analog to digital converter for converting output signals generated by respective photodetector circuits into digital image data; and

an image processor including a low-pass filter for filtering the digital image data to generate filtered image data.

6. A monolithic image sensing device including:

timing circuitry for generating at least one internal timing signal and at least one external timing signal;

an image sensor for sensing image data, the image sensor incorporating a plurality of photodetector circuits according to claim 1, and being responsive to at least one of the internal timing signals to commence sensing of the image data; and

at least one external pin for supplying the at least one external timing signal to at least one peripheral device.